github-wownero/RandomWOW
1
0
Fork 0
mirror of https://github.com/wownero/RandomWOW.git synced 2026-10-17 07:21:35 +02:00
Code Issues Packages Projects Releases Wiki Activity
466 Commits 10 Branches 5 Tags
5fc512e71ce91d8f1834e3f14c8fd335ed8a253f
Commit Graph
26 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
SChernykhandGitHub 5fc512e71c Merge pull request #282 from SChernykh/fix-ub 
Fixed UB in ARM64 JIT compiler
 2023-10-20 10:42:40 +02:00
SChernykh 8f91d31b8b Fixed UB in ARM64 JIT compiler 
Fixed unaligned memory writes
 2023-10-20 09:24:50 +02:00
SChernykhandGitHub d3c96482ee Merge pull request #281 from SChernykh/fix-x18 
ARM64 JIT: don't use `x18` register
 2023-10-19 22:00:34 +02:00
SChernykh f72101aa2c ARM64 JIT: don't use x18 register 2023-10-19 17:20:53 +02:00
SChernykhandtevador e322218fb7 Fixed casts from const to non-const pointers 2023-10-09 19:21:57 +02:00
SChernykhandGitHub 67ea010aa5 Merge pull request #273 from SChernykh/ci-test 
Added CI tests
 2023-08-24 15:41:55 +02:00
SChernykh 3f69ad7b79 Added CI tests 
- Compile RandomX on a wide variety of OS and architectures
- Fixed broken x86 (32-bit) builds
- Don't use broken `fesetenv` in msys2 builds: https://sourceforge.net/p/mingw-w64/bugs/541/
 2023-08-23 12:15:21 +02:00
SChernykhandGitHub 040f4500a6 Merge pull request #268 from SChernykh/fix_gcc13 
Fixed GCC 13 compilation
 2023-05-15 15:55:58 +02:00
SChernykh 43db7e290e Fixed GCC 13 compilation 2023-05-15 09:45:20 +02:00
SChernykhandGitHub 5bb4c7760d Merge pull request #259 from SChernykh/fix_invalidate_order 
Invalidate CPU I-cache on Apple Silicon
 2022-12-17 13:00:27 +01:00
SChernykh 7245f13c7e Invalidate CPU I-cache on Apple Silicon 
Call __builtin___clear_cache() after pthread_jit_write_protect_np() according to https://developer.apple.com/documentation/apple-silicon/porting-just-in-time-compilers-to-apple-silicon
 2022-11-30 13:26:20 +01:00
SChernykhandGitHub cced5cab2f Merge pull request #247 from SChernykh/fix_warning 
Fixed compiler warning
 2022-06-20 23:02:38 +02:00
SChernykh 00472c54ef Fixed compiler warning 
```
virtual_memory.c:210:14: warning: type defaults to 'int' in declaration of 'pageMinimum' [-Wimplicit-int]
```
 2022-06-04 19:47:17 +02:00
SChernykhandGitHub 09aa65c3c7 Merge pull request #246 from SChernykh/fix_leak 
Fixed cache->jit memory leak
 2022-05-25 09:12:36 +02:00
SChernykh 166e0d80f5 Fixed cache->jit memory leak 
1. `cache->jit = new randomx::JitCompiler();` - succeeds
2. `cache->memory = (uint8_t*)randomx::LargePageAllocator::allocMemory(randomx::CacheSize);` - fails
3. `if (cache && cache->memory == nullptr) randomx_release_cache(cache);` is executed
4. randomx_release_cache checks `if (cache->memory != nullptr)` and does nothing
5. cache->jit stays allocated
 2022-05-24 14:22:16 +02:00
SChernykhandGitHub ae8e98b681 Merge pull request #229 from tevador/pr-reserved 
Do not use reserved identifiers in intrin_portable.h
 2022-04-06 07:16:44 +02:00
SChernykh bbc9ccc90b Fixed a crash in MSVC Debug and RelWithDebInfo builds 
MSVC debug/relwithdebinfo builds use jmp trampolines for ASM functions, so these must be traversed to get the actual address of the code for each function.
 2021-11-06 22:15:07 +01:00
SChernykhandGitHub 3c8c7ee097 Optimized dataset read (#211) 
* Optimized dataset read

There was a false dependency on readReg2 and readReg3 (caused by `xor rbp, rax` instruction) when reading dataset item (see design.md - 4.6.2 Loop execution, steps 5 and 7). This change uses `ma` register to read dataset item before the whole `rbp` (`ma` and `mx`) is changed, so superscalar and out-of-order CPU can start executing it earlier.

Results: https://i.imgur.com/Bpeq9mx.png

~1% speedup on modern Intel/AMD CPUs.

* ARMv8: optimized dataset read

Break dependency from readReg2 and readReg3.

* Fixed light mode hashing
 2021-05-22 13:54:50 +02:00
SChernykh 2ba7df2844 Fix illegal instruction crash on some ARM systems 
See https://github.com/xmrig/xmrig/issues/1916
 2021-02-01 23:19:14 +01:00
SChernykhandtevador 219c02e1e5 Combined hash and fill AES loop (#166) 
Adds more parallelizm into AES loop so modern CPUs can take advantage of it. Also, scratchpad data moves between L1 and L3 caches only one time which saves time and energy per hash.
 2019-12-01 16:58:38 +01:00
SChernykh e43267fa86 Fix function names for clang on Apple 2019-11-12 13:04:11 +01:00
SChernykh 9a5d504bb3 Fix alignment for ARMv8 code 2019-10-19 00:20:09 +02:00
SChernykh 457c0e4a54 Workaround for gcc 8.3 on Arch Linux (ARM) 
ldr/madd instruction sequence makes compiled binary crash, so separate them.
 2019-09-23 22:23:23 +02:00
SChernykh 9e7ae84de4 Set scratchpad pointer to null by default 2019-09-23 15:56:14 +02:00
SChernykhandtevador c6468a3816 JIT compiler for ARMv8 (#125) 
JIT compiler for ARMv8
 2019-09-22 21:06:22 +02:00
SChernykh 93fec18991 Optimized loading from scratchpad 2019-09-11 11:48:22 +02:00