tevador f76e8c2e20 Reworked "FNEG" instruction to make ASIC optimizations more difficult

2019-02-13 00:01:34 +01:00

..

program_epilogue_linux.inc

Vector FPU instructions

2018-12-31 19:06:45 +01:00

program_epilogue_store.inc

Added explicit STORE instructions

2019-01-27 10:52:30 +01:00

program_epilogue_win64.inc

Added explicit STORE instructions

2019-01-27 10:52:30 +01:00

program_loop_load.inc

Added ISWAP instruction

2019-02-04 17:07:00 +01:00

program_loop_store.inc

Interpreter with bytecode

2019-02-09 15:45:26 +01:00

program_prologue_linux.inc

Position independent loads fixed #21

2019-02-11 18:13:03 +01:00

program_prologue_load.inc

Interpreter with bytecode

2019-02-09 15:45:26 +01:00

program_prologue_win64.inc

Position independent loads fixed #21

2019-02-11 18:13:03 +01:00

program_read_dataset.inc

Merged load/store of integer and FP registers

2019-01-27 19:33:55 +01:00

program_transform_address.inc

Reduced x86 code size by 512 bytes (and ecx -> and eax)

2019-01-12 20:27:35 +01:00

program_xmm_constants.inc

Reworked "FNEG" instruction to make ASIC optimizations more difficult

2019-02-13 00:01:34 +01:00

squareHash.inc

Added ISWAP instruction

2019-02-04 17:07:00 +01:00