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149 Commits 58 Branches 23 Tags
00368cae021232c5d96211ebc6dbfa4609d5d5f1
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5 Commits
Author SHA1 Message Date
tevador 20eb549725 Merged load/store of integer and FP registers 2019-01-27 19:33:55 +01:00
tevador 005c67f64c Added explicit STORE instructions 
JIT compiler
 2019-01-27 10:52:30 +01:00
tevador a7ffe8c19a Mix dataset cacheline with registers r0-r7 2019-01-13 21:14:59 +01:00
tevador d1a808643d Random accesses - JIT compiler 2019-01-10 22:04:55 +01:00
tevador 3caecc7646 Vector FPU instructions 
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
 2018-12-31 19:06:45 +01:00