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Reworked "FNEG" instruction to make ASIC optimizations more difficult

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This commit is contained in:
tevador
2019-02-13 00:01:34 +01:00
parent 376c868ca0
commit f76e8c2e20
11 changed files with 29 additions and 24 deletions
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src/JitCompilerX86.cpp
+2 -2
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@@ -605,7 +605,7 @@ namespace RandomX {
emitByte(0xc4 + 8 * instr.dst);
}
void JitCompilerX86::h_FNEG_R(Instruction& instr) {
void JitCompilerX86::h_FSCAL_R(Instruction& instr) {
instr.dst %= 4;
emit(REX_XORPS);
emitByte(0xc7 + 8 * instr.dst);
@@ -761,7 +761,7 @@ namespace RandomX {
INST_HANDLE(FADD_M)
INST_HANDLE(FSUB_R)
INST_HANDLE(FSUB_M)
INST_HANDLE(FNEG_R)
INST_HANDLE(FSCAL_R)
INST_HANDLE(FMUL_R)
INST_HANDLE(FMUL_M)
INST_HANDLE(FDIV_R)