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Use strongly typed enums (#55)

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This commit is contained in:
tevador
2019-06-10 16:02:25 +02:00
committed by GitHub
parent 52aa36249e
commit 447634f51d
7 changed files with 94 additions and 83 deletions
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src/superscalar.cpp
+28 -28
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@@ -40,7 +40,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
namespace randomx {
static bool isMultiplication(int type) {
static bool isMultiplication(SuperscalarInstructionType type) {
return type == SuperscalarInstructionType::IMUL_R || type == SuperscalarInstructionType::IMULH_R || type == SuperscalarInstructionType::ISMULH_R || type == SuperscalarInstructionType::IMUL_RCP;
}
@@ -167,7 +167,7 @@ namespace randomx {
const MacroOp& getOp(int index) const {
return ops_[index];
}
int getType() const {
SuperscalarInstructionType getType() const {
return type_;
}
int getResultOp() const {
@@ -196,7 +196,7 @@ namespace randomx {
static const SuperscalarInstructionInfo NOP;
private:
const char* name_;
int type_;
SuperscalarInstructionType type_;
std::vector<MacroOp> ops_;
int latency_;
int resultOp_ = 0;
@@ -204,13 +204,13 @@ namespace randomx {
int srcOp_;
SuperscalarInstructionInfo(const char* name)
: name_(name), type_(-1), latency_(0) {}
SuperscalarInstructionInfo(const char* name, int type, const MacroOp& op, int srcOp)
: name_(name), type_(SuperscalarInstructionType::INVALID), latency_(0) {}
SuperscalarInstructionInfo(const char* name, SuperscalarInstructionType type, const MacroOp& op, int srcOp)
: name_(name), type_(type), latency_(op.getLatency()), srcOp_(srcOp) {
ops_.push_back(MacroOp(op));
}
template <size_t N>
SuperscalarInstructionInfo(const char* name, int type, const MacroOp(&arr)[N], int resultOp, int dstOp, int srcOp)
SuperscalarInstructionInfo(const char* name, SuperscalarInstructionType type, const MacroOp(&arr)[N], int resultOp, int dstOp, int srcOp)
: name_(name), type_(type), latency_(0), resultOp_(resultOp), dstOp_(dstOp), srcOp_(srcOp) {
for (unsigned i = 0; i < N; ++i) {
ops_.push_back(MacroOp(arr[i]));
@@ -267,7 +267,7 @@ namespace randomx {
const char* getName() const {
return name_;
}
const DecoderBuffer* fetchNext(int instrType, int cycle, int mulCount, Blake2Generator& gen) const {
const DecoderBuffer* fetchNext(SuperscalarInstructionType instrType, int cycle, int mulCount, Blake2Generator& gen) const {
//If the current RandomX instruction is "IMULH", the next fetch configuration must be 3-3-10
//because the full 128-bit multiplication instruction is 3 bytes long and decodes to 2 uOPs on Intel CPUs.
//Intel CPUs can decode at most 4 uOPs per cycle, so this requires a 2-1-1 configuration for a total of 3 macro ops.
@@ -345,9 +345,9 @@ namespace randomx {
class RegisterInfo {
public:
RegisterInfo() : latency(0), lastOpGroup(-1), lastOpPar(-1), value(0) {}
RegisterInfo() : latency(0), lastOpGroup(SuperscalarInstructionType::INVALID), lastOpPar(-1), value(0) {}
int latency;
int lastOpGroup;
SuperscalarInstructionType lastOpGroup;
int lastOpPar;
int value;
};
@@ -356,7 +356,7 @@ namespace randomx {
class SuperscalarInstruction {
public:
void toInstr(Instruction& instr) { //translate to a RandomX instruction format
instr.opcode = getType();
instr.opcode = (int)getType();
instr.dst = dst_;
instr.src = src_ >= 0 ? src_ : dst_;
instr.setMod(mod_);
@@ -534,7 +534,7 @@ namespace randomx {
return false;
}
int getType() {
SuperscalarInstructionType getType() {
return info_->getType();
}
int getSource() {
@@ -543,7 +543,7 @@ namespace randomx {
int getDestination() {
return dst_;
}
int getGroup() {
SuperscalarInstructionType getGroup() {
return opGroup_;
}
int getGroupPar() {
@@ -562,7 +562,7 @@ namespace randomx {
int dst_ = -1;
int mod_;
uint32_t imm32_;
int opGroup_;
SuperscalarInstructionType opGroup_;
int opGroupPar_;
bool canReuse_ = false;
bool groupParIsSource_ = false;
@@ -849,40 +849,40 @@ namespace randomx {
void executeSuperscalar(int_reg_t(&r)[8], SuperscalarProgram& prog, std::vector<uint64_t> *reciprocals) {
for (unsigned j = 0; j < prog.getSize(); ++j) {
Instruction& instr = prog(j);
switch (instr.opcode)
switch ((SuperscalarInstructionType)instr.opcode)
{
case randomx::SuperscalarInstructionType::ISUB_R:
case SuperscalarInstructionType::ISUB_R:
r[instr.dst] -= r[instr.src];
break;
case randomx::SuperscalarInstructionType::IXOR_R:
case SuperscalarInstructionType::IXOR_R:
r[instr.dst] ^= r[instr.src];
break;
case randomx::SuperscalarInstructionType::IADD_RS:
case SuperscalarInstructionType::IADD_RS:
r[instr.dst] += r[instr.src] << instr.getModShift();
break;
case randomx::SuperscalarInstructionType::IMUL_R:
case SuperscalarInstructionType::IMUL_R:
r[instr.dst] *= r[instr.src];
break;
case randomx::SuperscalarInstructionType::IROR_C:
case SuperscalarInstructionType::IROR_C:
r[instr.dst] = rotr(r[instr.dst], instr.getImm32());
break;
case randomx::SuperscalarInstructionType::IADD_C7:
case randomx::SuperscalarInstructionType::IADD_C8:
case randomx::SuperscalarInstructionType::IADD_C9:
case SuperscalarInstructionType::IADD_C7:
case SuperscalarInstructionType::IADD_C8:
case SuperscalarInstructionType::IADD_C9:
r[instr.dst] += signExtend2sCompl(instr.getImm32());
break;
case randomx::SuperscalarInstructionType::IXOR_C7:
case randomx::SuperscalarInstructionType::IXOR_C8:
case randomx::SuperscalarInstructionType::IXOR_C9:
case SuperscalarInstructionType::IXOR_C7:
case SuperscalarInstructionType::IXOR_C8:
case SuperscalarInstructionType::IXOR_C9:
r[instr.dst] ^= signExtend2sCompl(instr.getImm32());
break;
case randomx::SuperscalarInstructionType::IMULH_R:
case SuperscalarInstructionType::IMULH_R:
r[instr.dst] = mulh(r[instr.dst], r[instr.src]);
break;
case randomx::SuperscalarInstructionType::ISMULH_R:
case SuperscalarInstructionType::ISMULH_R:
r[instr.dst] = smulh(r[instr.dst], r[instr.src]);
break;
case randomx::SuperscalarInstructionType::IMUL_RCP:
case SuperscalarInstructionType::IMUL_RCP:
if (reciprocals != nullptr)
r[instr.dst] *= (*reciprocals)[instr.getImm32()];
else