mirror of
https://github.com/wownero/RandomX.git
synced 2026-10-19 16:28:47 +02:00
Regression tests (#73)
* instruction decode/execute separated into class BytecodeMachine * added randomx-tests project * removed the use of non-portable __COUNTER__ macro * removed the use of unsupported FENV_ACCESS pragma
This commit is contained in:
tevador
+17
-563
@@ -39,8 +39,6 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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namespace randomx {
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static int_reg_t Zero = 0;
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::setDataset(randomx_dataset* dataset) {
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datasetPtr = dataset;
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@@ -54,223 +52,64 @@ namespace randomx {
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execute();
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}
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::executeBytecode(int_reg_t(&r)[RegistersCount], rx_vec_f128(&f)[RegisterCountFlt], rx_vec_f128(&e)[RegisterCountFlt], rx_vec_f128(&a)[RegisterCountFlt]) {
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for (int pc = 0; pc < RANDOMX_PROGRAM_SIZE; ++pc) {
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executeBytecode(pc, r, f, e, a);
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}
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}
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template<class Allocator, bool softAes>
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FORCE_INLINE void* InterpretedVm<Allocator, softAes>::getScratchpadAddress(InstructionByteCode& ibc) {
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uint32_t addr = (*ibc.isrc + ibc.imm) & ibc.memMask;
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return scratchpad + addr;
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}
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template<class Allocator, bool softAes>
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FORCE_INLINE rx_vec_f128 InterpretedVm<Allocator, softAes>::maskRegisterExponentMantissa(rx_vec_f128 x) {
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const rx_vec_f128 xmantissaMask = rx_set_vec_f128(dynamicMantissaMask, dynamicMantissaMask);
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const rx_vec_f128 xexponentMask = rx_load_vec_f128((const double*)&config.eMask);
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x = rx_and_vec_f128(x, xmantissaMask);
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x = rx_or_vec_f128(x, xexponentMask);
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return x;
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}
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::executeBytecode(int& pc, int_reg_t(&r)[RegistersCount], rx_vec_f128(&f)[RegisterCountFlt], rx_vec_f128(&e)[RegisterCountFlt], rx_vec_f128(&a)[RegisterCountFlt]) {
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auto& ibc = byteCode[pc];
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switch (ibc.type)
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{
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case InstructionType::IADD_RS: {
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*ibc.idst += (*ibc.isrc << ibc.shift) + ibc.imm;
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} break;
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case InstructionType::IADD_M: {
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*ibc.idst += load64(getScratchpadAddress(ibc));
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} break;
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case InstructionType::ISUB_R: {
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*ibc.idst -= *ibc.isrc;
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} break;
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case InstructionType::ISUB_M: {
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*ibc.idst -= load64(getScratchpadAddress(ibc));
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} break;
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case InstructionType::IMUL_R: { //also handles IMUL_RCP
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*ibc.idst *= *ibc.isrc;
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} break;
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case InstructionType::IMUL_M: {
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*ibc.idst *= load64(getScratchpadAddress(ibc));
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} break;
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case InstructionType::IMULH_R: {
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*ibc.idst = mulh(*ibc.idst, *ibc.isrc);
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} break;
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case InstructionType::IMULH_M: {
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*ibc.idst = mulh(*ibc.idst, load64(getScratchpadAddress(ibc)));
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} break;
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case InstructionType::ISMULH_R: {
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*ibc.idst = smulh(unsigned64ToSigned2sCompl(*ibc.idst), unsigned64ToSigned2sCompl(*ibc.isrc));
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} break;
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case InstructionType::ISMULH_M: {
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*ibc.idst = smulh(unsigned64ToSigned2sCompl(*ibc.idst), unsigned64ToSigned2sCompl(load64(getScratchpadAddress(ibc))));
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} break;
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case InstructionType::INEG_R: {
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*ibc.idst = ~(*ibc.idst) + 1; //two's complement negative
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} break;
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case InstructionType::IXOR_R: {
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*ibc.idst ^= *ibc.isrc;
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} break;
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case InstructionType::IXOR_M: {
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*ibc.idst ^= load64(getScratchpadAddress(ibc));
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} break;
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case InstructionType::IROR_R: {
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*ibc.idst = rotr(*ibc.idst, *ibc.isrc & 63);
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} break;
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case InstructionType::IROL_R: {
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*ibc.idst = rotl(*ibc.idst, *ibc.isrc & 63);
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} break;
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case InstructionType::ISWAP_R: {
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int_reg_t temp = *ibc.isrc;
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*ibc.isrc = *ibc.idst;
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*ibc.idst = temp;
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} break;
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case InstructionType::FSWAP_R: {
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*ibc.fdst = rx_swap_vec_f128(*ibc.fdst);
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} break;
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case InstructionType::FADD_R: {
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*ibc.fdst = rx_add_vec_f128(*ibc.fdst, *ibc.fsrc);
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} break;
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case InstructionType::FADD_M: {
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rx_vec_f128 fsrc = rx_cvt_packed_int_vec_f128(getScratchpadAddress(ibc));
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*ibc.fdst = rx_add_vec_f128(*ibc.fdst, fsrc);
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} break;
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case InstructionType::FSUB_R: {
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*ibc.fdst = rx_sub_vec_f128(*ibc.fdst, *ibc.fsrc);
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} break;
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case InstructionType::FSUB_M: {
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rx_vec_f128 fsrc = rx_cvt_packed_int_vec_f128(getScratchpadAddress(ibc));
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*ibc.fdst = rx_sub_vec_f128(*ibc.fdst, fsrc);
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} break;
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case InstructionType::FSCAL_R: {
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const rx_vec_f128 mask = rx_set1_vec_f128(0x80F0000000000000);
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*ibc.fdst = rx_xor_vec_f128(*ibc.fdst, mask);
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} break;
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case InstructionType::FMUL_R: {
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*ibc.fdst = rx_mul_vec_f128(*ibc.fdst, *ibc.fsrc);
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} break;
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case InstructionType::FDIV_M: {
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rx_vec_f128 fsrc = maskRegisterExponentMantissa(rx_cvt_packed_int_vec_f128(getScratchpadAddress(ibc)));
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*ibc.fdst = rx_div_vec_f128(*ibc.fdst, fsrc);
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} break;
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case InstructionType::FSQRT_R: {
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*ibc.fdst = rx_sqrt_vec_f128(*ibc.fdst);
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} break;
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case InstructionType::CBRANCH: {
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*ibc.isrc += ibc.imm;
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if ((*ibc.isrc & ibc.memMask) == 0) {
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pc = ibc.target;
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}
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} break;
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case InstructionType::CFROUND: {
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rx_set_rounding_mode(rotr(*ibc.isrc, ibc.imm) % 4);
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} break;
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case InstructionType::ISTORE: {
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store64(scratchpad + ((*ibc.idst + ibc.imm) & ibc.memMask), *ibc.isrc);
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} break;
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case InstructionType::NOP: {
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//nothing
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} break;
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default:
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UNREACHABLE;
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}
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}
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::execute() {
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int_reg_t r[RegistersCount] = { 0 };
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rx_vec_f128 f[RegisterCountFlt];
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rx_vec_f128 e[RegisterCountFlt];
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rx_vec_f128 a[RegisterCountFlt];
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NativeRegisterFile nreg;
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for(unsigned i = 0; i < RegisterCountFlt; ++i)
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a[i] = rx_load_vec_f128(®.a[i].lo);
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nreg.a[i] = rx_load_vec_f128(®.a[i].lo);
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precompileProgram(r, f, e, a);
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compileProgram(program, bytecode, nreg);
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uint32_t spAddr0 = mem.mx;
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uint32_t spAddr1 = mem.ma;
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for(unsigned ic = 0; ic < RANDOMX_PROGRAM_ITERATIONS; ++ic) {
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uint64_t spMix = r[config.readReg0] ^ r[config.readReg1];
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uint64_t spMix = nreg.r[config.readReg0] ^ nreg.r[config.readReg1];
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spAddr0 ^= spMix;
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spAddr0 &= ScratchpadL3Mask64;
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spAddr1 ^= spMix >> 32;
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spAddr1 &= ScratchpadL3Mask64;
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for (unsigned i = 0; i < RegistersCount; ++i)
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r[i] ^= load64(scratchpad + spAddr0 + 8 * i);
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nreg.r[i] ^= load64(scratchpad + spAddr0 + 8 * i);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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f[i] = rx_cvt_packed_int_vec_f128(scratchpad + spAddr1 + 8 * i);
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nreg.f[i] = rx_cvt_packed_int_vec_f128(scratchpad + spAddr1 + 8 * i);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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e[i] = maskRegisterExponentMantissa(rx_cvt_packed_int_vec_f128(scratchpad + spAddr1 + 8 * (RegisterCountFlt + i)));
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nreg.e[i] = maskRegisterExponentMantissa(config, rx_cvt_packed_int_vec_f128(scratchpad + spAddr1 + 8 * (RegisterCountFlt + i)));
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executeBytecode(r, f, e, a);
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executeBytecode(bytecode, scratchpad, config);
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mem.mx ^= r[config.readReg2] ^ r[config.readReg3];
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mem.mx ^= nreg.r[config.readReg2] ^ nreg.r[config.readReg3];
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mem.mx &= CacheLineAlignMask;
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datasetPrefetch(datasetOffset + mem.mx);
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datasetRead(datasetOffset + mem.ma, r);
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datasetRead(datasetOffset + mem.ma, nreg.r);
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std::swap(mem.mx, mem.ma);
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for (unsigned i = 0; i < RegistersCount; ++i)
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store64(scratchpad + spAddr1 + 8 * i, r[i]);
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store64(scratchpad + spAddr1 + 8 * i, nreg.r[i]);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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f[i] = rx_xor_vec_f128(f[i], e[i]);
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nreg.f[i] = rx_xor_vec_f128(nreg.f[i], nreg.e[i]);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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rx_store_vec_f128((double*)(scratchpad + spAddr0 + 16 * i), f[i]);
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rx_store_vec_f128((double*)(scratchpad + spAddr0 + 16 * i), nreg.f[i]);
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spAddr0 = 0;
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spAddr1 = 0;
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}
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for (unsigned i = 0; i < RegistersCount; ++i)
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store64(®.r[i], r[i]);
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store64(®.r[i], nreg.r[i]);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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rx_store_vec_f128(®.f[i].lo, f[i]);
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rx_store_vec_f128(®.f[i].lo, nreg.f[i]);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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rx_store_vec_f128(®.e[i].lo, e[i]);
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rx_store_vec_f128(®.e[i].lo, nreg.e[i]);
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}
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template<class Allocator, bool softAes>
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@@ -285,391 +124,6 @@ namespace randomx {
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rx_prefetch_nta(mem.memory + address);
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}
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#include "instruction_weights.hpp"
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::precompileProgram(int_reg_t(&r)[RegistersCount], rx_vec_f128(&f)[RegisterCountFlt], rx_vec_f128(&e)[RegisterCountFlt], rx_vec_f128(&a)[RegisterCountFlt]) {
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int registerUsage[RegistersCount];
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for (unsigned i = 0; i < RegistersCount; ++i) {
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registerUsage[i] = -1;
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}
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for (unsigned i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) {
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auto& instr = program(i);
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auto& ibc = byteCode[i];
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switch (instr.opcode) {
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CASE_REP(IADD_RS) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IADD_RS;
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ibc.idst = &r[dst];
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if (dst != RegisterNeedsDisplacement) {
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ibc.isrc = &r[src];
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ibc.shift = instr.getModShift();
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ibc.imm = 0;
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}
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else {
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ibc.isrc = &r[src];
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ibc.shift = instr.getModShift();
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ibc.imm = signExtend2sCompl(instr.getImm32());
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(IADD_M) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IADD_M;
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ibc.idst = &r[dst];
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ibc.imm = signExtend2sCompl(instr.getImm32());
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if (src != dst) {
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ibc.isrc = &r[src];
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ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
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}
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else {
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ibc.isrc = &Zero;
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ibc.memMask = ScratchpadL3Mask;
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(ISUB_R) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::ISUB_R;
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ibc.idst = &r[dst];
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if (src != dst) {
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ibc.isrc = &r[src];
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}
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else {
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ibc.imm = signExtend2sCompl(instr.getImm32());
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ibc.isrc = &ibc.imm;
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(ISUB_M) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::ISUB_M;
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ibc.idst = &r[dst];
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ibc.imm = signExtend2sCompl(instr.getImm32());
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if (src != dst) {
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ibc.isrc = &r[src];
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ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
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}
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else {
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ibc.isrc = &Zero;
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ibc.memMask = ScratchpadL3Mask;
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(IMUL_R) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IMUL_R;
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ibc.idst = &r[dst];
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if (src != dst) {
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ibc.isrc = &r[src];
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}
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else {
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ibc.imm = signExtend2sCompl(instr.getImm32());
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ibc.isrc = &ibc.imm;
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(IMUL_M) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IMUL_M;
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ibc.idst = &r[dst];
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ibc.imm = signExtend2sCompl(instr.getImm32());
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if (src != dst) {
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ibc.isrc = &r[src];
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ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
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}
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else {
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ibc.isrc = &Zero;
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ibc.memMask = ScratchpadL3Mask;
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(IMULH_R) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IMULH_R;
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ibc.idst = &r[dst];
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ibc.isrc = &r[src];
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registerUsage[dst] = i;
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} break;
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CASE_REP(IMULH_M) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IMULH_M;
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ibc.idst = &r[dst];
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ibc.imm = signExtend2sCompl(instr.getImm32());
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if (src != dst) {
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ibc.isrc = &r[src];
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ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
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}
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else {
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ibc.isrc = &Zero;
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ibc.memMask = ScratchpadL3Mask;
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(ISMULH_R) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::ISMULH_R;
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ibc.idst = &r[dst];
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ibc.isrc = &r[src];
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registerUsage[dst] = i;
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} break;
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CASE_REP(ISMULH_M) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::ISMULH_M;
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ibc.idst = &r[dst];
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ibc.imm = signExtend2sCompl(instr.getImm32());
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if (src != dst) {
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ibc.isrc = &r[src];
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ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
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}
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else {
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ibc.isrc = &Zero;
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ibc.memMask = ScratchpadL3Mask;
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||||
}
|
||||
registerUsage[dst] = i;
|
||||
} break;
|
||||
|
||||
CASE_REP(IMUL_RCP) {
|
||||
uint64_t divisor = instr.getImm32();
|
||||
if (!isPowerOf2(divisor)) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
ibc.type = InstructionType::IMUL_R;
|
||||
ibc.idst = &r[dst];
|
||||
ibc.imm = randomx_reciprocal(divisor);
|
||||
ibc.isrc = &ibc.imm;
|
||||
registerUsage[dst] = i;
|
||||
}
|
||||
else {
|
||||
ibc.type = InstructionType::NOP;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(INEG_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
ibc.type = InstructionType::INEG_R;
|
||||
ibc.idst = &r[dst];
|
||||
registerUsage[dst] = i;
|
||||
} break;
|
||||
|
||||
CASE_REP(IXOR_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::IXOR_R;
|
||||
ibc.idst = &r[dst];
|
||||
if (src != dst) {
|
||||
ibc.isrc = &r[src];
|
||||
}
|
||||
else {
|
||||
ibc.imm = signExtend2sCompl(instr.getImm32());
|
||||
ibc.isrc = &ibc.imm;
|
||||
}
|
||||
registerUsage[dst] = i;
|
||||
} break;
|
||||
|
||||
CASE_REP(IXOR_M) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::IXOR_M;
|
||||
ibc.idst = &r[dst];
|
||||
ibc.imm = signExtend2sCompl(instr.getImm32());
|
||||
if (src != dst) {
|
||||
ibc.isrc = &r[src];
|
||||
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
}
|
||||
else {
|
||||
ibc.isrc = &Zero;
|
||||
ibc.memMask = ScratchpadL3Mask;
|
||||
}
|
||||
registerUsage[dst] = i;
|
||||
} break;
|
||||
|
||||
CASE_REP(IROR_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::IROR_R;
|
||||
ibc.idst = &r[dst];
|
||||
if (src != dst) {
|
||||
ibc.isrc = &r[src];
|
||||
}
|
||||
else {
|
||||
ibc.imm = instr.getImm32();
|
||||
ibc.isrc = &ibc.imm;
|
||||
}
|
||||
registerUsage[dst] = i;
|
||||
} break;
|
||||
|
||||
CASE_REP(IROL_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::IROL_R;
|
||||
ibc.idst = &r[dst];
|
||||
if (src != dst) {
|
||||
ibc.isrc = &r[src];
|
||||
}
|
||||
else {
|
||||
ibc.imm = instr.getImm32();
|
||||
ibc.isrc = &ibc.imm;
|
||||
}
|
||||
registerUsage[dst] = i;
|
||||
} break;
|
||||
|
||||
CASE_REP(ISWAP_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
if (src != dst) {
|
||||
ibc.idst = &r[dst];
|
||||
ibc.isrc = &r[src];
|
||||
ibc.type = InstructionType::ISWAP_R;
|
||||
registerUsage[dst] = i;
|
||||
registerUsage[src] = i;
|
||||
}
|
||||
else {
|
||||
ibc.type = InstructionType::NOP;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(FSWAP_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
ibc.type = InstructionType::FSWAP_R;
|
||||
if (dst < RegisterCountFlt)
|
||||
ibc.fdst = &f[dst];
|
||||
else
|
||||
ibc.fdst = &e[dst - RegisterCountFlt];
|
||||
} break;
|
||||
|
||||
CASE_REP(FADD_R) {
|
||||
auto dst = instr.dst % RegisterCountFlt;
|
||||
auto src = instr.src % RegisterCountFlt;
|
||||
ibc.type = InstructionType::FADD_R;
|
||||
ibc.fdst = &f[dst];
|
||||
ibc.fsrc = &a[src];
|
||||
} break;
|
||||
|
||||
CASE_REP(FADD_M) {
|
||||
auto dst = instr.dst % RegisterCountFlt;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::FADD_M;
|
||||
ibc.fdst = &f[dst];
|
||||
ibc.isrc = &r[src];
|
||||
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
ibc.imm = signExtend2sCompl(instr.getImm32());
|
||||
} break;
|
||||
|
||||
CASE_REP(FSUB_R) {
|
||||
auto dst = instr.dst % RegisterCountFlt;
|
||||
auto src = instr.src % RegisterCountFlt;
|
||||
ibc.type = InstructionType::FSUB_R;
|
||||
ibc.fdst = &f[dst];
|
||||
ibc.fsrc = &a[src];
|
||||
} break;
|
||||
|
||||
CASE_REP(FSUB_M) {
|
||||
auto dst = instr.dst % RegisterCountFlt;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::FSUB_M;
|
||||
ibc.fdst = &f[dst];
|
||||
ibc.isrc = &r[src];
|
||||
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
ibc.imm = signExtend2sCompl(instr.getImm32());
|
||||
} break;
|
||||
|
||||
CASE_REP(FSCAL_R) {
|
||||
auto dst = instr.dst % RegisterCountFlt;
|
||||
ibc.fdst = &f[dst];
|
||||
ibc.type = InstructionType::FSCAL_R;
|
||||
} break;
|
||||
|
||||
CASE_REP(FMUL_R) {
|
||||
auto dst = instr.dst % RegisterCountFlt;
|
||||
auto src = instr.src % RegisterCountFlt;
|
||||
ibc.type = InstructionType::FMUL_R;
|
||||
ibc.fdst = &e[dst];
|
||||
ibc.fsrc = &a[src];
|
||||
} break;
|
||||
|
||||
CASE_REP(FDIV_M) {
|
||||
auto dst = instr.dst % RegisterCountFlt;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::FDIV_M;
|
||||
ibc.fdst = &e[dst];
|
||||
ibc.isrc = &r[src];
|
||||
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
ibc.imm = signExtend2sCompl(instr.getImm32());
|
||||
} break;
|
||||
|
||||
CASE_REP(FSQRT_R) {
|
||||
auto dst = instr.dst % RegisterCountFlt;
|
||||
ibc.type = InstructionType::FSQRT_R;
|
||||
ibc.fdst = &e[dst];
|
||||
} break;
|
||||
|
||||
CASE_REP(CBRANCH) {
|
||||
ibc.type = InstructionType::CBRANCH;
|
||||
//jump condition
|
||||
int reg = instr.dst % RegistersCount;
|
||||
ibc.isrc = &r[reg];
|
||||
ibc.target = registerUsage[reg];
|
||||
int shift = instr.getModCond() + ConditionOffset;
|
||||
const uint64_t conditionMask = ConditionMask << shift;
|
||||
ibc.imm = signExtend2sCompl(instr.getImm32()) | (1ULL << shift);
|
||||
if (ConditionOffset > 0 || shift > 0) //clear the bit below the condition mask - this limits the number of successive jumps to 2
|
||||
ibc.imm &= ~(1ULL << (shift - 1));
|
||||
ibc.memMask = ConditionMask << shift;
|
||||
//mark all registers as used
|
||||
for (unsigned j = 0; j < RegistersCount; ++j) {
|
||||
registerUsage[j] = i;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(CFROUND) {
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.isrc = &r[src];
|
||||
ibc.type = InstructionType::CFROUND;
|
||||
ibc.imm = instr.getImm32() & 63;
|
||||
} break;
|
||||
|
||||
CASE_REP(ISTORE) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::ISTORE;
|
||||
ibc.idst = &r[dst];
|
||||
ibc.isrc = &r[src];
|
||||
ibc.imm = signExtend2sCompl(instr.getImm32());
|
||||
if (instr.getModCond() < StoreL3Condition)
|
||||
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
else
|
||||
ibc.memMask = ScratchpadL3Mask;
|
||||
} break;
|
||||
|
||||
CASE_REP(NOP) {
|
||||
ibc.type = InstructionType::NOP;
|
||||
} break;
|
||||
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
template class InterpretedVm<AlignedAllocator<CacheLineSize>, false>;
|
||||
template class InterpretedVm<AlignedAllocator<CacheLineSize>, true>;
|
||||
template class InterpretedVm<LargePageAllocator, false>;
|
||||
|
||||
Reference in New Issue
Block a user