tevadorandGitHub 91cd35ff13 Decrease the frequency of FADD/FSUB in favor of FMUL (#77) ...

* this better matches CPU capabilities since execution ports are usually split 1:1 between fadd and fmul
* the frequency of FSWAP_R decreased from 8 to 4 (it's ASIC-friendly)
* activate IROL_R instruction

2019-06-22 16:05:22 +02:00

..

configuration.asm

Decrease the frequency of FADD/FSUB in favor of FMUL (#77)

2019-06-22 16:05:22 +02:00

program_epilogue_linux.inc

Fix build on Cygwin/MinGW

2019-05-18 19:30:28 +02:00

program_epilogue_store.inc

Added explicit STORE instructions

2019-01-27 10:52:30 +01:00

program_epilogue_win64.inc

Fix build on Cygwin/MinGW

2019-05-18 19:30:28 +02:00

program_loop_load.inc

Use values from configuration.h in assembly code

2019-05-06 18:14:00 +02:00

program_loop_store.inc

CompiledLightVirtualMachine

2019-03-21 20:44:59 +01:00

program_prologue_linux.inc

Fix build on Cygwin/MinGW

2019-05-18 19:30:28 +02:00

program_prologue_win64.inc

Fix build on Cygwin/MinGW

2019-05-18 19:30:28 +02:00

program_read_dataset_sshash_fin.inc

SuperscalarHash interpreter

2019-04-11 00:01:22 +02:00

program_read_dataset_sshash_init.inc

Use values from configuration.h in assembly code

2019-05-06 18:14:00 +02:00

program_read_dataset.inc

Use values from configuration.h in assembly code

2019-05-06 18:14:00 +02:00

program_sshash_constants.inc

Dataset size increased to 2080 MiB

2019-04-26 16:05:30 +02:00

program_sshash_load.inc

Fixed cache alignment

2019-04-06 17:07:40 +02:00

program_sshash_prefetch.inc

Use values from configuration.h in assembly code

2019-05-06 18:14:00 +02:00

program_xmm_constants.inc

Fixed FSCAL instruction causing group F registers to exceed their intended maximum value

2019-05-15 22:07:26 +02:00

randomx_reciprocal.inc

30% faster JIT compiler

2019-05-04 19:40:25 +02:00