mirror of
https://github.com/wownero/RandomWOW.git
synced 2026-10-17 15:31:46 +02:00
Fixed mining and verification mode not giving the same results
Trace support in Assembly generator
This commit is contained in:
tevador
@@ -82,6 +82,31 @@ namespace RandomX {
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void InterpretedVirtualMachine::executeBytecode<ProgramLength>(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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}
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static void print(int_reg_t r) {
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std::cout << std::hex << std::setw(16) << std::setfill('0') << r << std::endl;
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}
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static void print(__m128d f) {
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uint64_t lo = *(((uint64_t*)&f) + 0);
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uint64_t hi = *(((uint64_t*)&f) + 1);
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std::cout << std::hex << std::setw(16) << std::setfill('0') << hi << '-' << std::hex << std::setw(16) << std::setfill('0') << lo << std::endl;
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}
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static void printState(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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for (int i = 0; i < 8; ++i) {
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std::cout << "r" << i << " = "; print(r[i]);
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}
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for (int i = 0; i < 4; ++i) {
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std::cout << "f" << i << " = "; print(f[i]);
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}
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for (int i = 0; i < 4; ++i) {
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std::cout << "e" << i << " = "; print(e[i]);
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}
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for (int i = 0; i < 4; ++i) {
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std::cout << "a" << i << " = "; print(a[i]);
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}
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}
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FORCE_INLINE void InterpretedVirtualMachine::executeBytecode(int i, int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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auto& ibc = byteCode[i];
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switch (ibc.type)
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@@ -107,7 +132,7 @@ namespace RandomX {
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} break;
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case InstructionType::IMUL_9C: {
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*ibc.idst += 9 * *ibc.idst + ibc.imm;
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*ibc.idst += 8 * *ibc.idst + ibc.imm;
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} break;
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case InstructionType::IMUL_R: {
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@@ -210,7 +235,7 @@ namespace RandomX {
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} break;
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case InstructionType::FDIV_M: {
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__m128d fsrc = load_cvt_i32x2(scratchpad + (*ibc.isrc & ibc.memMask));
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__m128d fsrc = _mm_abs(load_cvt_i32x2(scratchpad + (*ibc.isrc & ibc.memMask)));
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__m128d fdst = _mm_div_pd(*ibc.fdst, fsrc);
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*ibc.fdst = _mm_max_pd(fdst, _mm_set_pd(DBL_MIN, DBL_MIN));
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} break;
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@@ -220,11 +245,11 @@ namespace RandomX {
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} break;
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case InstructionType::COND_R: {
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*ibc.idst += condition(*ibc.isrc, ibc.imm, ibc.condition) ? 1 : 0;
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*ibc.idst += condition(ibc.condition, *ibc.isrc, ibc.imm) ? 1 : 0;
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} break;
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case InstructionType::COND_M: {
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*ibc.idst += condition(load64(scratchpad + (*ibc.isrc & ibc.memMask)), ibc.imm, ibc.condition) ? 1 : 0;
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*ibc.idst += condition(ibc.condition, load64(scratchpad + (*ibc.isrc & ibc.memMask)), ibc.imm) ? 1 : 0;
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} break;
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case InstructionType::CFROUND: {
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@@ -242,6 +267,13 @@ namespace RandomX {
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default:
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UNREACHABLE;
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}
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if (trace) {
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//std::cout << program(i);
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if(ibc.type < 20 || ibc.type == 31 || ibc.type == 32)
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print(*ibc.idst);
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else //if(ibc.type >= 20 && ibc.type <= 30)
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print(0);
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}
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}
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void InterpretedVirtualMachine::execute() {
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@@ -260,10 +292,20 @@ namespace RandomX {
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uint32_t spAddr0 = mem.mx;
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uint32_t spAddr1 = mem.ma;
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if (trace) {
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std::cout << "execute (reg: r" << readReg0 << ", r" << readReg1 << ", r" << readReg2 << ", r" << readReg3 << ")" << std::endl;
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std::cout << "spAddr " << std::hex << std::setw(8) << std::setfill('0') << spAddr1 << " / " << std::setw(8) << std::setfill('0') << spAddr0 << std::endl;
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std::cout << "ma/mx " << std::hex << std::setw(8) << std::setfill('0') << mem.ma << std::setw(8) << std::setfill('0') << mem.mx << std::endl;
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printState(r, f, e, a);
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}
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for(unsigned iter = 0; iter < InstructionCount; ++iter) {
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//std::cout << "Iteration " << iter << std::endl;
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spAddr0 ^= r[readReg0];
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uint64_t spMix = r[readReg0] ^ r[readReg1];
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spAddr0 ^= spMix;
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spAddr0 &= ScratchpadL3Mask64;
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spAddr1 ^= spMix >> 32;
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spAddr1 &= ScratchpadL3Mask64;
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r[0] ^= load64(scratchpad + spAddr0 + 0);
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r[1] ^= load64(scratchpad + spAddr0 + 8);
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@@ -274,9 +316,6 @@ namespace RandomX {
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r[6] ^= load64(scratchpad + spAddr0 + 48);
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r[7] ^= load64(scratchpad + spAddr0 + 56);
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spAddr1 ^= r[readReg1];
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spAddr1 &= ScratchpadL3Mask64;
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f[0] = load_cvt_i32x2(scratchpad + spAddr1 + 0);
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f[1] = load_cvt_i32x2(scratchpad + spAddr1 + 8);
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f[2] = load_cvt_i32x2(scratchpad + spAddr1 + 16);
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@@ -286,6 +325,14 @@ namespace RandomX {
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e[2] = _mm_abs(load_cvt_i32x2(scratchpad + spAddr1 + 48));
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e[3] = _mm_abs(load_cvt_i32x2(scratchpad + spAddr1 + 56));
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if (trace) {
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std::cout << "iteration " << std::dec << iter << std::endl;
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std::cout << "spAddr " << std::hex << std::setw(8) << std::setfill('0') << spAddr1 << " / " << std::setw(8) << std::setfill('0') << spAddr0 << std::endl;
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std::cout << "ma/mx " << std::hex << std::setw(8) << std::setfill('0') << mem.ma << std::setw(8) << std::setfill('0') << mem.mx << std::endl;
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printState(r, f, e, a);
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std::cout << "-----------------------------------" << std::endl;
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}
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executeBytecode<0>(r, f, e, a);
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if (asyncWorker) {
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@@ -309,6 +356,14 @@ namespace RandomX {
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std::swap(mem.mx, mem.ma);
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}
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if (trace) {
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std::cout << "iteration " << std::dec << iter << std::endl;
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std::cout << "spAddr " << std::hex << std::setw(8) << std::setfill('0') << spAddr1 << " / " << std::setw(8) << std::setfill('0') << spAddr0 << std::endl;
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std::cout << "ma/mx " << std::hex << std::setw(8) << std::setfill('0') << mem.ma << std::setw(8) << std::setfill('0') << mem.mx << std::endl;
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printState(r, f, e, a);
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std::cout << "===================================" << std::endl;
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}
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store64(scratchpad + spAddr1 + 0, r[0]);
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store64(scratchpad + spAddr1 + 8, r[1]);
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store64(scratchpad + spAddr1 + 16, r[2]);
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@@ -318,10 +373,15 @@ namespace RandomX {
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store64(scratchpad + spAddr1 + 48, r[6]);
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store64(scratchpad + spAddr1 + 56, r[7]);
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_mm_store_pd((double*)(scratchpad + spAddr0 + 0), _mm_mul_pd(f[0], e[0]));
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_mm_store_pd((double*)(scratchpad + spAddr0 + 16), _mm_mul_pd(f[1], e[1]));
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_mm_store_pd((double*)(scratchpad + spAddr0 + 32), _mm_mul_pd(f[2], e[2]));
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_mm_store_pd((double*)(scratchpad + spAddr0 + 48), _mm_mul_pd(f[3], e[3]));
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f[0] = _mm_mul_pd(f[0], e[0]);
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f[1] = _mm_mul_pd(f[1], e[1]);
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f[2] = _mm_mul_pd(f[2], e[2]);
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f[3] = _mm_mul_pd(f[3], e[3]);
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_mm_store_pd((double*)(scratchpad + spAddr0 + 0), f[0]);
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_mm_store_pd((double*)(scratchpad + spAddr0 + 16), f[1]);
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_mm_store_pd((double*)(scratchpad + spAddr0 + 32), f[2]);
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_mm_store_pd((double*)(scratchpad + spAddr0 + 48), f[3]);
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spAddr0 = 0;
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spAddr1 = 0;
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@@ -719,6 +779,7 @@ namespace RandomX {
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ibc.type = InstructionType::ISTORE;
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ibc.idst = &r[dst];
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ibc.isrc = &r[src];
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ibc.memMask = ((instr.mod % 4) ? ScratchpadL1Mask : ScratchpadL2Mask);
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} break;
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CASE_REP(FSTORE) {
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