mirror of
https://github.com/wownero/RandomWOW.git
synced 2026-10-17 23:41:36 +02:00
Added branches - ASM and JIT only
This commit is contained in:
tevador
@@ -18,6 +18,7 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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*/
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//#define TRACE
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#include <climits>
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#include "AssemblyGeneratorX86.hpp"
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#include "common.hpp"
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#include "reciprocal.h"
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@@ -45,9 +46,25 @@ namespace RandomX {
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static const char* regDatasetAddr = "rdi";
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static const char* regScratchpadAddr = "rsi";
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int AssemblyGeneratorX86::getConditionRegister() {
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int min = INT_MAX;
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int minIndex;
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for (unsigned i = 0; i < 8; ++i) {
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if (registerUsage[i] < min) {
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min = registerUsage[i];
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minIndex = i;
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}
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}
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return minIndex;
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}
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void AssemblyGeneratorX86::generateProgram(Program& prog) {
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for (unsigned i = 0; i < 8; ++i) {
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registerUsage[i] = -1;
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}
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asmCode.str(std::string()); //clear
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for (unsigned i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) {
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asmCode << "randomx_isn_" << i << ":" << std::endl;
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Instruction& instr = prog(i);
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instr.src %= RegistersCount;
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instr.dst %= RegistersCount;
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@@ -96,6 +113,7 @@ namespace RandomX {
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//1 uOP
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void AssemblyGeneratorX86::h_IADD_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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asmCode << "\tadd " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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@@ -107,6 +125,7 @@ namespace RandomX {
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//2.75 uOP
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void AssemblyGeneratorX86::h_IADD_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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@@ -119,12 +138,14 @@ namespace RandomX {
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//1 uOP
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void AssemblyGeneratorX86::h_IADD_RC(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_ISUB_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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asmCode << "\tsub " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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@@ -136,6 +157,7 @@ namespace RandomX {
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//2.75 uOP
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void AssemblyGeneratorX86::h_ISUB_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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@@ -148,12 +170,14 @@ namespace RandomX {
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//1 uOP
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void AssemblyGeneratorX86::h_IMUL_9C(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.dst] << "*8" << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IMUL_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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asmCode << "\timul " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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@@ -165,6 +189,7 @@ namespace RandomX {
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//2.75 uOP
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void AssemblyGeneratorX86::h_IMUL_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\timul " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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@@ -177,6 +202,7 @@ namespace RandomX {
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//4 uOPs
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void AssemblyGeneratorX86::h_IMULH_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\tmul " << regR[instr.src] << std::endl;
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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@@ -185,6 +211,7 @@ namespace RandomX {
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//5.75 uOPs
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void AssemblyGeneratorX86::h_IMULH_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr, "ecx");
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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@@ -200,6 +227,7 @@ namespace RandomX {
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//4 uOPs
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void AssemblyGeneratorX86::h_ISMULH_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\timul " << regR[instr.src] << std::endl;
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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@@ -208,6 +236,7 @@ namespace RandomX {
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//5.75 uOPs
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void AssemblyGeneratorX86::h_ISMULH_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr, "ecx");
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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@@ -223,12 +252,14 @@ namespace RandomX {
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//1 uOP
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void AssemblyGeneratorX86::h_INEG_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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asmCode << "\tneg " << regR[instr.dst] << std::endl;
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IXOR_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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asmCode << "\txor " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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@@ -240,6 +271,7 @@ namespace RandomX {
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//2.75 uOP
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void AssemblyGeneratorX86::h_IXOR_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\txor " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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@@ -252,6 +284,7 @@ namespace RandomX {
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//1.75 uOPs
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void AssemblyGeneratorX86::h_IROR_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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asmCode << "\tmov ecx, " << regR32[instr.src] << std::endl;
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asmCode << "\tror " << regR[instr.dst] << ", cl" << std::endl;
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@@ -264,6 +297,7 @@ namespace RandomX {
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//1.75 uOPs
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void AssemblyGeneratorX86::h_IROL_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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asmCode << "\tmov ecx, " << regR32[instr.src] << std::endl;
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asmCode << "\trol " << regR[instr.dst] << ", cl" << std::endl;
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@@ -277,6 +311,7 @@ namespace RandomX {
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//2 uOPs
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void AssemblyGeneratorX86::h_IMUL_RCP(Instruction& instr, int i) {
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if (instr.getImm32() != 0) {
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registerUsage[instr.dst] = i;
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uint32_t divisor = instr.getImm32();
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asmCode << "\tmov rax, " << reciprocal(instr.getImm32()) << std::endl;
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asmCode << "\timul " << regR[instr.dst] << ", rax" << std::endl;
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@@ -295,6 +330,9 @@ namespace RandomX {
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//2 uOPs
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void AssemblyGeneratorX86::h_ISWAP_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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//std::swap(registerUsage[instr.dst], registerUsage[instr.src]);
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registerUsage[instr.dst] = i;
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registerUsage[instr.src] = i;
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asmCode << "\txchg " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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traceint(instr);
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}
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@@ -435,8 +473,23 @@ namespace RandomX {
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}
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}
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void AssemblyGeneratorX86::handleCondition(Instruction& instr, int i) {
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const int shift = (instr.mod >> 5);
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const int conditionMask = ((1 << RANDOMX_CONDITION_BITS) - 1) << shift;
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int reg = getConditionRegister();
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int target = registerUsage[reg] + 1;
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registerUsage[reg] = i;
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asmCode << "\tadd " << regR[reg] << ", " << (1 << shift) << std::endl;
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asmCode << "\ttest " << regR[reg] << ", " << conditionMask << std::endl;
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asmCode << "\tjz randomx_isn_" << target << std::endl;
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for (unsigned j = 0; j < 8; ++j) { //mark all registers as used
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registerUsage[j] = i;
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}
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}
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//4 uOPs
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void AssemblyGeneratorX86::h_COND_R(Instruction& instr, int i) {
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handleCondition(instr, i);
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asmCode << "\txor ecx, ecx" << std::endl;
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asmCode << "\tcmp " << regR32[instr.src] << ", " << (int32_t)instr.getImm32() << std::endl;
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asmCode << "\tset" << condition(instr) << " cl" << std::endl;
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@@ -446,6 +499,7 @@ namespace RandomX {
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//6 uOPs
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void AssemblyGeneratorX86::h_COND_M(Instruction& instr, int i) {
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handleCondition(instr, i);
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asmCode << "\txor ecx, ecx" << std::endl;
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genAddressReg(instr);
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asmCode << "\tcmp dword ptr [rsi+rax], " << (int32_t)instr.getImm32() << std::endl;
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