tevador
|
8f2abd6c05
|
NOP instruction
register load/store from L3
|
2019-01-27 18:19:49 +01:00 |
|
tevador
|
005c67f64c
|
Added explicit STORE instructions
JIT compiler
|
2019-01-27 10:52:30 +01:00 |
|
tevador
|
bd0dba88a8
|
4 scratchpad segments
|
2019-01-20 00:44:01 +01:00 |
|
tevador
|
a7ffe8c19a
|
Mix dataset cacheline with registers r0-r7
|
2019-01-13 21:14:59 +01:00 |
|
tevador
|
67e741ff22
|
Reduced x86 code size by 512 bytes (and ecx -> and eax)
|
2019-01-12 20:27:35 +01:00 |
|
tevador
|
d1a808643d
|
Random accesses - JIT compiler
|
2019-01-10 22:04:55 +01:00 |
|
tevador
|
b6d654291f
|
90 address transformations
|
2019-01-08 12:19:19 +01:00 |
|
tevador
|
3caecc7646
|
Vector FPU instructions
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
|
2018-12-31 19:06:45 +01:00 |
|