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https://codeberg.org/wownero/RandomX.git
synced 2026-10-17 05:41:32 +02:00
ASM code generator for "small" programs that fit into the uOP cache
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tevador
@@ -130,333 +130,10 @@ namespace RandomX {
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#endif
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}
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convertible_t InterpretedVirtualMachine::loada(Instruction& instr) {
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convertible_t& rega = reg.r[instr.rega % RegistersCount];
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rega.i64 ^= instr.addra; //sign-extend addra
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addr_t addr = rega.u32;
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if ((ic % 64) == 0) {
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addr = currentTransform->apply(addr);
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#ifdef STATS
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datasetAccess[mem.ma / (DatasetBlockCount / 256) / CacheLineSize]++;
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#endif
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readDataset(addr, mem, reg);
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}
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if ((instr.loca & 192) == 0) {
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mem.mx ^= addr;
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}
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if (instr.loca & 3) {
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return scratchpad[addr % ScratchpadL1];
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}
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else {
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return scratchpad[addr % ScratchpadL2];
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}
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}
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convertible_t InterpretedVirtualMachine::loadbia(Instruction& instr) {
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if (instr.locb & 3) {
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return reg.r[instr.regb % RegistersCount];
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}
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else {
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convertible_t temp;
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temp.i64 = instr.imm32; //sign-extend imm32
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return temp;
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}
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}
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convertible_t InterpretedVirtualMachine::loadbiashift(Instruction& instr) {
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if (instr.locb & 1) {
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return reg.r[instr.regb % RegistersCount];
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}
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else {
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convertible_t temp;
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temp.u64 = instr.imm8;
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return temp;
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}
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}
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convertible_t InterpretedVirtualMachine::loadbiadiv(Instruction& instr) {
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if (instr.locb & 3) {
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convertible_t temp;
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temp.u64 = instr.imm32;
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return temp;
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}
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else {
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return reg.r[instr.regb % RegistersCount];
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}
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}
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convertible_t& InterpretedVirtualMachine::getcr(Instruction& inst) {
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addr_t addr;
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switch (inst.locc & 7)
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{
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case 0:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addrc;
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return scratchpad[addr % ScratchpadL2];
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case 1:
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case 2:
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case 3:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addrc;
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return scratchpad[addr % ScratchpadL1];
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case 4:
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case 5:
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case 6:
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case 7:
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return reg.r[inst.regc % RegistersCount];
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}
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}
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void InterpretedVirtualMachine::writecf(Instruction& inst, fpu_reg_t& regc) {
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addr_t addr;
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switch (inst.locc & 7)
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{
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case 4:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addrc;
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scratchpad[addr % ScratchpadL2] = (inst.locc & 8) ? regc.hi : regc.lo;
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break;
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case 5:
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case 6:
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case 7:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addrc;
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scratchpad[addr % ScratchpadL1] = (inst.locc & 8) ? regc.hi : regc.lo;
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default:
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break;
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}
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}
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#define ALU_RETIRE(x) x(a, b, c); \
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if(trace) std::cout << std::hex << /*a.u64 << " " << b.u64 << " " <<*/ c.u64 << std::endl;
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#define CHECK_NOP_FPDIV(b, c)
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#ifndef STATS
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#define CHECK_NOP_FPADD(b, c)
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#define CHECK_NOP_FPSUB(b, c)
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#define CHECK_NOP_FPMUL(b, c)
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#else
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#define CHECK_NOP_FPADD(b, c) bool loeq = (b.lo.u64 == c.lo.u64); bool hieq = (b.hi.u64 == c.hi.u64); count_FPADD_nop += loeq + hieq; if(loeq && hieq) count_FPADD_nop2++;
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#define CHECK_NOP_FPSUB(b, c) bool loeq = ((b.lo.u64 & INT64_MAX) == (c.lo.u64 & INT64_MAX)); bool hieq = ((b.hi.u64 & INT64_MAX) == (c.hi.u64 & INT64_MAX)); count_FPSUB_nop += loeq + hieq; if(loeq && hieq) count_FPSUB_nop2++;
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#define CHECK_NOP_FPMUL(b, c) bool loeq = (b.lo.u64 == c.lo.u64); bool hieq = (b.hi.u64 == c.hi.u64); count_FPMUL_nop += loeq + hieq; if(loeq && hieq) count_FPMUL_nop2++;
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#endif
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#define FPU_RETIRE(x) x(a, b, c); \
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writecf(inst, c); \
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if(trace) { \
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std::cout << std::hex << ((inst.locc & 8) ? c.hi.u64 : c.lo.u64) << std::endl; \
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} \
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if(fpuCheck) { \
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if(c.hi.f64 != c.hi.f64 || c.lo.f64 != c.lo.f64) { \
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std::stringstream ss; \
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ss << "NaN result of " << #x << "(" << std::hex << a.u64 << ", " << b.hi.u64 << " " << b.lo.u64 << ") = " << c.hi.u64 << " " << c.lo.u64 << std::endl; \
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throw std::runtime_error(ss.str()); \
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} else if (std::fpclassify(c.hi.f64) == FP_SUBNORMAL || std::fpclassify(c.lo.f64) == FP_SUBNORMAL) {\
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std::stringstream ss; \
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ss << "Denormal result of " << #x << "(" << std::hex << a.u64 << ", " << b.hi.u64 << " " << b.lo.u64 << ") = " << c.hi.u64 << " " << c.lo.u64 << std::endl; \
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throw std::runtime_error(ss.str()); \
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} \
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}
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#ifdef STATS
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#define INC_COUNT(x) count_##x++;
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#else
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#define INC_COUNT(x)
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#endif
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#define FPU_RETIRE_FPSQRT(x) FPSQRT(a, b, c); \
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writecf(inst, c); \
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if(trace) std::cout << std::hex << ((inst.locc & 8) ? c.hi.u64 : c.lo.u64) << std::endl;
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#define FPU_RETIRE_FPROUND(x) FPROUND(a, b, c); \
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writecflo(inst, c); \
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if(trace) std::cout << std::hex << c.lo.u64 << std::endl;
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#define ALU_INST(x) void InterpretedVirtualMachine::h_##x(Instruction& inst) { \
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INC_COUNT(x) \
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convertible_t a = loada(inst); \
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convertible_t b = loadbia(inst); \
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convertible_t& c = getcr(inst); \
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ALU_RETIRE(x) \
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}
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#define ALU_INST_SR(x) void InterpretedVirtualMachine::h_##x(Instruction& inst) { \
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INC_COUNT(x) \
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convertible_t a = loada(inst); \
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convertible_t b = loadbiashift(inst); \
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convertible_t& c = getcr(inst); \
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ALU_RETIRE(x) \
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}
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#define ALU_INST_DIV(x) void InterpretedVirtualMachine::h_##x(Instruction& inst) { \
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INC_COUNT(x) \
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convertible_t a = loada(inst); \
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convertible_t b = loadbiadiv(inst); \
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convertible_t& c = getcr(inst); \
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ALU_RETIRE(x) \
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}
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#define FPU_INST(x) void InterpretedVirtualMachine::h_##x(Instruction& inst) { \
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INC_COUNT(x) \
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convertible_t a = loada(inst); \
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fpu_reg_t& b = reg.f[inst.regb % RegistersCount]; \
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fpu_reg_t btemp = b; \
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fpu_reg_t& c = reg.f[inst.regc % RegistersCount]; \
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FPU_RETIRE(x) \
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CHECK_NOP_##x(btemp, c) \
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}
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#define FPU_INST_NB(x) void InterpretedVirtualMachine::h_##x(Instruction& inst) { \
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INC_COUNT(x) \
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convertible_t a = loada(inst); \
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fpu_reg_t b; \
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fpu_reg_t& c = reg.f[inst.regc % RegistersCount]; \
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FPU_RETIRE_##x(x) \
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}
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ALU_INST(ADD_64)
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ALU_INST(ADD_32)
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ALU_INST(SUB_64)
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ALU_INST(SUB_32)
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ALU_INST(MUL_64)
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ALU_INST(MULH_64)
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ALU_INST(MUL_32)
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ALU_INST(IMUL_32)
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ALU_INST(IMULH_64)
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ALU_INST_DIV(DIV_64)
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ALU_INST_DIV(IDIV_64)
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ALU_INST(AND_64)
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ALU_INST(AND_32)
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ALU_INST(OR_64)
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ALU_INST(OR_32)
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ALU_INST(XOR_64)
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ALU_INST(XOR_32)
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ALU_INST_SR(SHL_64)
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ALU_INST_SR(SHR_64)
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ALU_INST_SR(SAR_64)
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ALU_INST_SR(ROL_64)
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ALU_INST_SR(ROR_64)
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FPU_INST(FPADD)
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FPU_INST(FPSUB)
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FPU_INST(FPMUL)
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FPU_INST(FPDIV)
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FPU_INST_NB(FPSQRT)
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void InterpretedVirtualMachine::h_FPROUND(Instruction& inst) {
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convertible_t a = loada(inst);
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convertible_t& c = getcr(inst);
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c.u64 = a.u64;
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if (trace) std::cout << std::hex << a.u64 << std::endl;
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FPROUND(a, inst.imm8);
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}
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void InterpretedVirtualMachine::h_JUMP(Instruction& inst) {
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convertible_t a = loada(inst);
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convertible_t& c = getcr(inst);
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c.u64 = a.u64;
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if (trace) std::cout << std::hex << a.u64 << std::endl;
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if (JMP_COND(inst.locb, reg.r[inst.regb % RegistersCount], inst.imm32)) {
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#ifdef STATS
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count_JUMP_taken++;
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count_jump_taken[inst.locb & 7]++;
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#endif
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pc += (inst.imm8 & 127) + 1;
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pc = pc % ProgramLength;
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}
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#ifdef STATS
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else {
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count_JUMP_not_taken++;
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count_jump_not_taken[inst.locb & 7]++;
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}
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#endif
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}
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void InterpretedVirtualMachine::h_CALL(Instruction& inst) {
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convertible_t a = loada(inst);
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convertible_t& c = getcr(inst);
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c.u64 = a.u64;
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if (trace) std::cout << std::hex << a.u64 << std::endl;
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if (JMP_COND(inst.locb, reg.r[inst.regb % RegistersCount], inst.imm32)) {
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#ifdef STATS
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count_CALL_taken++;
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count_jump_taken[inst.locb & 7]++;
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count_retdepth = std::max(0, count_retdepth - 1);
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#endif
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stackPush(pc);
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#ifdef STATS
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count_max_stack = std::max(count_max_stack, (int)stack.size());
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#endif
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pc += (inst.imm8 & 127) + 1;
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pc = pc % ProgramLength;
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}
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#ifdef STATS
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else {
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count_CALL_not_taken++;
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count_jump_not_taken[inst.locb & 7]++;
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}
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#endif
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}
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void InterpretedVirtualMachine::h_RET(Instruction& inst) {
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convertible_t a = loada(inst);
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convertible_t& c = getcr(inst);
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c.u64 = a.u64;
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if (trace) std::cout << std::hex << a.u64 << std::endl;
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if (stack.size() > 0) {
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#ifdef STATS
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count_RET_taken++;
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count_retdepth++;
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count_retdepth_max = std::max(count_retdepth_max, count_retdepth);
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#endif
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auto raddr = stackPopAddress();
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pc = raddr;
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}
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#ifdef STATS
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else {
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count_RET_stack_empty++;
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}
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#endif
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}
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#include "instructionWeights.hpp"
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#define INST_HANDLE(x) REPN(&InterpretedVirtualMachine::h_##x, WT(x))
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InstructionHandler InterpretedVirtualMachine::engine[256] = {
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INST_HANDLE(ADD_64)
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INST_HANDLE(ADD_32)
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INST_HANDLE(SUB_64)
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INST_HANDLE(SUB_32)
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INST_HANDLE(MUL_64)
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INST_HANDLE(MULH_64)
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INST_HANDLE(MUL_32)
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INST_HANDLE(IMUL_32)
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INST_HANDLE(IMULH_64)
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INST_HANDLE(DIV_64)
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INST_HANDLE(IDIV_64)
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INST_HANDLE(AND_64)
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INST_HANDLE(AND_32)
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INST_HANDLE(OR_64)
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INST_HANDLE(OR_32)
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INST_HANDLE(XOR_64)
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INST_HANDLE(XOR_32)
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INST_HANDLE(SHL_64)
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INST_HANDLE(SHR_64)
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INST_HANDLE(SAR_64)
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INST_HANDLE(ROL_64)
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INST_HANDLE(ROR_64)
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INST_HANDLE(FPADD)
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INST_HANDLE(FPSUB)
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INST_HANDLE(FPMUL)
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INST_HANDLE(FPDIV)
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INST_HANDLE(FPSQRT)
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INST_HANDLE(FPROUND)
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INST_HANDLE(JUMP)
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INST_HANDLE(CALL)
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INST_HANDLE(RET)
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};
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}
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