Commit Graph
8 Commits
Author SHA1 Message Date
SChernykhandGitHub 3c8c7ee097 Optimized dataset read (#211)
* Optimized dataset read

There was a false dependency on readReg2 and readReg3 (caused by `xor rbp, rax` instruction) when reading dataset item (see design.md - 4.6.2 Loop execution, steps 5 and 7). This change uses `ma` register to read dataset item before the whole `rbp` (`ma` and `mx`) is changed, so superscalar and out-of-order CPU can start executing it earlier.

Results: https://i.imgur.com/Bpeq9mx.png

~1% speedup on modern Intel/AMD CPUs.

* ARMv8: optimized dataset read

Break dependency from readReg2 and readReg3.

* Fixed light mode hashing
2021-05-22 13:54:50 +02:00
tevador 1276d67d2f Fix build on Cygwin/MinGW 2019-05-18 19:30:28 +02:00
tevador d9bc6cfeda Updated JIT compiler and assembly generator for new int -> float conversion 2019-02-24 17:24:06 +01:00
tevador 69764966c0 Position independent loads fixed #21 2019-02-11 18:13:03 +01:00
tevador 20eb549725 Merged load/store of integer and FP registers 2019-01-27 19:33:55 +01:00
tevador 005c67f64c Added explicit STORE instructions
JIT compiler
2019-01-27 10:52:30 +01:00
tevador d1a808643d Random accesses - JIT compiler 2019-01-10 22:04:55 +01:00
tevador 3caecc7646 Vector FPU instructions
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
2018-12-31 19:06:45 +01:00