mirror of
https://codeberg.org/wownero/RandomWOW.git
synced 2026-10-19 05:58:37 +02:00
Reworked SuperscalarHash instruction set
ASM and C code generator for SuperscalarHash Support for Superscalar hash in the light mode
This commit is contained in:
tevador
@@ -23,6 +23,7 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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#include "common.hpp"
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#include "reciprocal.h"
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#include "Program.hpp"
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#include "./LightProgramGenerator.hpp"
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namespace RandomX {
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@@ -46,6 +47,179 @@ namespace RandomX {
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static const char* regDatasetAddr = "rdi";
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static const char* regScratchpadAddr = "rsi";
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void AssemblyGeneratorX86::generateProgram(Program& prog) {
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for (unsigned i = 0; i < 8; ++i) {
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registerUsage[i] = -1;
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}
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asmCode.str(std::string()); //clear
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for (unsigned i = 0; i < prog.getSize(); ++i) {
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asmCode << "randomx_isn_" << i << ":" << std::endl;
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Instruction& instr = prog(i);
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instr.src %= RegistersCount;
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instr.dst %= RegistersCount;
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generateCode(instr, i);
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//asmCode << std::endl;
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}
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}
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void AssemblyGeneratorX86::generateAsm(LightProgram& prog) {
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asmCode.str(std::string()); //clear
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asmCode << "ALIGN 16" << std::endl;
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for (unsigned i = 0; i < prog.getSize(); ++i) {
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Instruction& instr = prog(i);
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switch (instr.opcode)
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{
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case RandomX::LightInstructionType::ISUB_R:
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asmCode << "sub " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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break;
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case RandomX::LightInstructionType::IXOR_R:
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asmCode << "xor " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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break;
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case RandomX::LightInstructionType::IADD_RS:
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asmCode << "lea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.mod % 4)) << "]" << std::endl;
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break;
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case RandomX::LightInstructionType::IMUL_R:
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asmCode << "imul " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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break;
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case RandomX::LightInstructionType::IROR_C:
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asmCode << "ror " << regR[instr.dst] << ", " << instr.getImm32() << std::endl;
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break;
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case RandomX::LightInstructionType::IADD_C7:
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asmCode << "add " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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break;
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case RandomX::LightInstructionType::IXOR_C7:
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asmCode << "xor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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break;
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case RandomX::LightInstructionType::IADD_C8:
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asmCode << "add " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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asmCode << "nop" << std::endl;
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break;
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case RandomX::LightInstructionType::IXOR_C8:
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asmCode << "xor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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asmCode << "nop" << std::endl;
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break;
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case RandomX::LightInstructionType::IADD_C9:
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asmCode << "add " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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asmCode << "xchg ax, ax ;nop" << std::endl;
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break;
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case RandomX::LightInstructionType::IXOR_C9:
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asmCode << "xor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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asmCode << "xchg ax, ax ;nop" << std::endl;
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break;
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case RandomX::LightInstructionType::IMULH_R:
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asmCode << "mov rax, " << regR[instr.dst] << std::endl;
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asmCode << "mul " << regR[instr.src] << std::endl;
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asmCode << "mov " << regR[instr.dst] << ", rdx" << std::endl;
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break;
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case RandomX::LightInstructionType::ISMULH_R:
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asmCode << "mov rax, " << regR[instr.dst] << std::endl;
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asmCode << "imul " << regR[instr.src] << std::endl;
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asmCode << "mov " << regR[instr.dst] << ", rdx" << std::endl;
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break;
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case RandomX::LightInstructionType::IMUL_RCP:
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asmCode << "mov rax, " << (int64_t)reciprocal(instr.getImm32()) << std::endl;
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asmCode << "imul " << regR[instr.dst] << ", rax" << std::endl;
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break;
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default:
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UNREACHABLE;
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}
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}
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}
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void AssemblyGeneratorX86::generateC(LightProgram& prog) {
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asmCode.str(std::string()); //clear
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asmCode << "#include <stdint.h>" << std::endl;
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asmCode << "#if defined(__SIZEOF_INT128__)" << std::endl;
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asmCode << " static inline uint64_t mulh(uint64_t a, uint64_t b) {" << std::endl;
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asmCode << " return ((unsigned __int128)a * b) >> 64;" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " static inline int64_t smulh(int64_t a, int64_t b) {" << std::endl;
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asmCode << " return ((__int128)a * b) >> 64;" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_MULH" << std::endl;
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asmCode << " #define HAVE_SMULH" << std::endl;
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asmCode << "#endif" << std::endl;
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asmCode << "#if defined(_MSC_VER)" << std::endl;
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asmCode << " #define HAS_VALUE(X) X ## 0" << std::endl;
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asmCode << " #define EVAL_DEFINE(X) HAS_VALUE(X)" << std::endl;
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asmCode << " #include <intrin.h>" << std::endl;
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asmCode << " #include <stdlib.h>" << std::endl;
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asmCode << " static __inline uint64_t rotr(uint64_t x , int c) {" << std::endl;
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asmCode << " return _rotr64(x, c);" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_ROTR" << std::endl;
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asmCode << " #if EVAL_DEFINE(__MACHINEARM64_X64(1))" << std::endl;
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asmCode << " static __inline uint64_t mulh(uint64_t a, uint64_t b) {" << std::endl;
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asmCode << " return __umulh(a, b);" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_MULH" << std::endl;
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asmCode << " #endif" << std::endl;
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asmCode << " #if EVAL_DEFINE(__MACHINEX64(1))" << std::endl;
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asmCode << " static __inline int64_t smulh(int64_t a, int64_t b) {" << std::endl;
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asmCode << " int64_t hi;" << std::endl;
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asmCode << " _mul128(a, b, &hi);" << std::endl;
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asmCode << " return hi;" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_SMULH" << std::endl;
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asmCode << " #endif" << std::endl;
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asmCode << "#endif" << std::endl;
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asmCode << "#ifndef HAVE_ROTR" << std::endl;
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asmCode << " static inline uint64_t rotr(uint64_t a, int b) {" << std::endl;
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asmCode << " return (a >> b) | (a << (64 - b));" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_ROTR" << std::endl;
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asmCode << "#endif" << std::endl;
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asmCode << "#if !defined(HAVE_MULH) || !defined(HAVE_SMULH) || !defined(HAVE_ROTR)" << std::endl;
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asmCode << " #error \"Required functions are not defined\"" << std::endl;
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asmCode << "#endif" << std::endl;
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asmCode << "void superScalar(uint64_t r[8]) {" << std::endl;
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asmCode << "uint64_t r8 = r[0], r9 = r[1], r10 = r[2], r11 = r[3], r12 = r[4], r13 = r[5], r14 = r[6], r15 = r[7];" << std::endl;
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for (unsigned i = 0; i < prog.getSize(); ++i) {
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Instruction& instr = prog(i);
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switch (instr.opcode)
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{
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case RandomX::LightInstructionType::ISUB_R:
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asmCode << regR[instr.dst] << " -= " << regR[instr.src] << ";" << std::endl;
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break;
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case RandomX::LightInstructionType::IXOR_R:
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asmCode << regR[instr.dst] << " ^= " << regR[instr.src] << ";" << std::endl;
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break;
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case RandomX::LightInstructionType::IADD_RS:
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asmCode << regR[instr.dst] << " += " << regR[instr.src] << "*" << (1 << (instr.mod % 4)) << ";" << std::endl;
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break;
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case RandomX::LightInstructionType::IMUL_R:
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asmCode << regR[instr.dst] << " *= " << regR[instr.src] << ";" << std::endl;
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break;
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case RandomX::LightInstructionType::IROR_C:
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asmCode << regR[instr.dst] << " = rotr(" << regR[instr.dst] << ", " << instr.getImm32() << ");" << std::endl;
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break;
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case RandomX::LightInstructionType::IADD_C7:
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case RandomX::LightInstructionType::IADD_C8:
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case RandomX::LightInstructionType::IADD_C9:
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asmCode << regR[instr.dst] << " += " << (int32_t)instr.getImm32() << ";" << std::endl;
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break;
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case RandomX::LightInstructionType::IXOR_C7:
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case RandomX::LightInstructionType::IXOR_C8:
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case RandomX::LightInstructionType::IXOR_C9:
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asmCode << regR[instr.dst] << " ^= " << (int32_t)instr.getImm32() << ";" << std::endl;
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break;
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case RandomX::LightInstructionType::IMULH_R:
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asmCode << regR[instr.dst] << " = mulh(" << regR[instr.dst] << ", " << regR[instr.src] << ");" << std::endl;
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break;
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case RandomX::LightInstructionType::ISMULH_R:
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asmCode << regR[instr.dst] << " = smulh(" << regR[instr.dst] << ", " << regR[instr.src] << ");" << std::endl;
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break;
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case RandomX::LightInstructionType::IMUL_RCP:
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asmCode << regR[instr.dst] << " *= " << (int64_t)reciprocal(instr.getImm32()) << ";" << std::endl;
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break;
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default:
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UNREACHABLE;
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}
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}
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asmCode << "r[0] = r8; r[1] = r9; r[2] = r10; r[3] = r11; r[4] = r12; r[5] = r13; r[6] = r14; r[7] = r15;" << std::endl;
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asmCode << "}" << std::endl;
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}
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int AssemblyGeneratorX86::getConditionRegister() {
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int min = INT_MAX;
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int minIndex;
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