mirror of
https://codeberg.org/wownero/RandomWOW.git
synced 2026-10-17 05:41:31 +02:00
SuperscalarHash interpreter
Linux assembly code
This commit is contained in:
tevador
@@ -36,6 +36,7 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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#ifdef STATS
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#include <algorithm>
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#endif
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#include "LightProgramGenerator.hpp"
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#ifdef FPUCHECK
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constexpr bool fpuCheck = true;
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@@ -45,17 +46,20 @@ constexpr bool fpuCheck = false;
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namespace RandomX {
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InterpretedVirtualMachine::~InterpretedVirtualMachine() {
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}
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void InterpretedVirtualMachine::setDataset(dataset_t ds, uint64_t size, LightProgram(&programs)[RANDOMX_CACHE_ACCESSES]) {
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template<bool superscalar>
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void InterpretedVirtualMachine<superscalar>::setDataset(dataset_t ds, uint64_t size, LightProgram(&programs)[RANDOMX_CACHE_ACCESSES]) {
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mem.ds = ds;
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readDataset = &datasetReadLight;
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datasetRange = (size - RANDOMX_DATASET_SIZE + CacheLineSize) / CacheLineSize;
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if(superscalar)
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precompileSuperscalar(programs);
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}
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void InterpretedVirtualMachine::initialize() {
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template void InterpretedVirtualMachine<true>::setDataset(dataset_t ds, uint64_t size, LightProgram(&programs)[RANDOMX_CACHE_ACCESSES]);
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template void InterpretedVirtualMachine<false>::setDataset(dataset_t ds, uint64_t size, LightProgram(&programs)[RANDOMX_CACHE_ACCESSES]);
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template<bool superscalar>
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void InterpretedVirtualMachine<superscalar>::initialize() {
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VirtualMachine::initialize();
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for (unsigned i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) {
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program(i).src %= RegistersCount;
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@@ -63,12 +67,19 @@ namespace RandomX {
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}
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}
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void InterpretedVirtualMachine::executeBytecode(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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template void InterpretedVirtualMachine<true>::initialize();
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template void InterpretedVirtualMachine<false>::initialize();
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template<bool superscalar>
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void InterpretedVirtualMachine<superscalar>::executeBytecode(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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for (int ic = 0; ic < RANDOMX_PROGRAM_SIZE; ++ic) {
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executeBytecode(ic, r, f, e, a);
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}
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}
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template void InterpretedVirtualMachine<true>::executeBytecode(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]);
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template void InterpretedVirtualMachine<false>::executeBytecode(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]);
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static void print(int_reg_t r) {
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std::cout << std::hex << std::setw(16) << std::setfill('0') << r << std::endl;
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}
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@@ -98,14 +109,15 @@ namespace RandomX {
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return std::fpclassify(x) == FP_SUBNORMAL;
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}
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FORCE_INLINE void InterpretedVirtualMachine::executeBytecode(int& ic, int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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template<bool superscalar>
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FORCE_INLINE void InterpretedVirtualMachine<superscalar>::executeBytecode(int& ic, int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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auto& ibc = byteCode[ic];
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if (trace) std::cout << std::dec << std::setw(3) << ic << " " << program(ic);
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//if(trace) printState(r, f, e, a);
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switch (ibc.type)
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{
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case InstructionType::IADD_R: {
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*ibc.idst += *ibc.isrc;
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case InstructionType::IADD_RS: {
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*ibc.idst += (*ibc.isrc << ibc.shift) + ibc.imm;
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} break;
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case InstructionType::IADD_M: {
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@@ -289,7 +301,8 @@ namespace RandomX {
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#endif
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}
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void InterpretedVirtualMachine::execute() {
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template<bool superscalar>
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void InterpretedVirtualMachine<superscalar>::execute() {
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int_reg_t r[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
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__m128d f[4];
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__m128d e[4];
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@@ -350,11 +363,16 @@ namespace RandomX {
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mem.mx ^= r[readReg2] ^ r[readReg3];
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mem.mx &= CacheLineAlignMask;
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Cache& cache = mem.ds.cache;
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uint64_t datasetLine[CacheLineSize / sizeof(uint64_t)];
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initBlock(cache, (uint8_t*)datasetLine, datasetBase + mem.ma / CacheLineSize, RANDOMX_CACHE_ACCESSES / 8);
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for (int i = 0; i < RegistersCount; ++i)
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r[i] ^= datasetLine[i];
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if (superscalar) {
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executeSuperscalar(datasetBase + mem.ma / CacheLineSize, r);
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}
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else {
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Cache& cache = mem.ds.cache;
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uint64_t datasetLine[CacheLineSize / sizeof(uint64_t)];
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initBlock(cache, (uint8_t*)datasetLine, datasetBase + mem.ma / CacheLineSize, RANDOMX_CACHE_ACCESSES / 8);
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for (int i = 0; i < RegistersCount; ++i)
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r[i] ^= datasetLine[i];
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}
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std::swap(mem.mx, mem.ma);
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if (trace) {
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@@ -419,6 +437,9 @@ namespace RandomX {
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_mm_store_pd(®.e[3].lo, e[3]);
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}
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template void InterpretedVirtualMachine<true>::execute();
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template void InterpretedVirtualMachine<false>::execute();
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static int getConditionRegister(int(®isterUsage)[8]) {
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int min = INT_MAX;
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int minIndex;
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@@ -431,9 +452,118 @@ namespace RandomX {
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return minIndex;
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}
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constexpr uint64_t superscalarMul0 = 6364136223846793005ULL;
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constexpr uint64_t superscalarAdd1 = 9298410992540426048ULL;
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constexpr uint64_t superscalarAdd2 = 12065312585734608966ULL;
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constexpr uint64_t superscalarAdd3 = 9306329213124610396ULL;
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constexpr uint64_t superscalarAdd4 = 5281919268842080866ULL;
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constexpr uint64_t superscalarAdd5 = 10536153434571861004ULL;
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constexpr uint64_t superscalarAdd6 = 3398623926847679864ULL;
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constexpr uint64_t superscalarAdd7 = 9549104520008361294ULL;
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static uint8_t* getMixBlock(uint64_t registerValue, Cache& cache) {
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uint8_t* mixBlock;
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if (RANDOMX_ARGON_GROWTH == 0) {
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constexpr uint32_t mask = (RANDOMX_ARGON_MEMORY * ArgonBlockSize / CacheLineSize - 1);
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mixBlock = cache.memory + (registerValue & mask) * CacheLineSize;
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}
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else {
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const uint32_t modulus = cache.size / CacheLineSize;
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mixBlock = cache.memory + (registerValue % modulus) * CacheLineSize;
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}
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return mixBlock;
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}
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template<bool superscalar>
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void InterpretedVirtualMachine<superscalar>::executeSuperscalar(uint32_t blockNumber, int_reg_t(&r)[8]) {
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int_reg_t rl[8];
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uint8_t* mixBlock;
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uint64_t registerValue = blockNumber;
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rl[0] = (blockNumber + 1) * superscalarMul0;
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rl[1] = rl[0] ^ superscalarAdd1;
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rl[2] = rl[0] ^ superscalarAdd2;
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rl[3] = rl[0] ^ superscalarAdd3;
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rl[4] = rl[0] ^ superscalarAdd4;
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rl[5] = rl[0] ^ superscalarAdd5;
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rl[6] = rl[0] ^ superscalarAdd6;
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rl[7] = rl[0] ^ superscalarAdd7;
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Cache& cache = mem.ds.cache;
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for (unsigned i = 0; i < RANDOMX_CACHE_ACCESSES; ++i) {
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mixBlock = getMixBlock(registerValue, cache);
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LightProgram& prog = superScalarPrograms[i];
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for (unsigned j = 0; j < prog.getSize(); ++j) {
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Instruction& instr = prog(j);
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switch (instr.opcode)
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{
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case RandomX::LightInstructionType::ISUB_R:
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rl[instr.dst] -= rl[instr.src];
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break;
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case RandomX::LightInstructionType::IXOR_R:
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rl[instr.dst] ^= rl[instr.src];
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break;
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case RandomX::LightInstructionType::IADD_RS:
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rl[instr.dst] += rl[instr.src] << (instr.mod % 4);
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break;
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case RandomX::LightInstructionType::IMUL_R:
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rl[instr.dst] *= rl[instr.src];
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break;
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case RandomX::LightInstructionType::IROR_C:
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rl[instr.dst] = rotr(rl[instr.dst], instr.getImm32());
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break;
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case RandomX::LightInstructionType::IADD_C7:
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case RandomX::LightInstructionType::IADD_C8:
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case RandomX::LightInstructionType::IADD_C9:
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rl[instr.dst] += signExtend2sCompl(instr.getImm32());
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break;
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case RandomX::LightInstructionType::IXOR_C7:
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case RandomX::LightInstructionType::IXOR_C8:
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case RandomX::LightInstructionType::IXOR_C9:
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rl[instr.dst] ^= signExtend2sCompl(instr.getImm32());
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break;
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case RandomX::LightInstructionType::IMULH_R:
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rl[instr.dst] = mulh(rl[instr.dst], rl[instr.src]);
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break;
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case RandomX::LightInstructionType::ISMULH_R:
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rl[instr.dst] = smulh(rl[instr.dst], rl[instr.src]);
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break;
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case RandomX::LightInstructionType::IMUL_RCP:
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rl[instr.dst] *= reciprocals[instr.getImm32()];
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break;
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default:
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UNREACHABLE;
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}
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}
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for(unsigned q = 0; q < 8; ++q)
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rl[q] ^= load64(mixBlock + 8 * q);
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registerValue = rl[prog.getAddressRegister()];
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}
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for (unsigned q = 0; q < 8; ++q)
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r[q] ^= rl[q];
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}
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template<bool superscalar>
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void InterpretedVirtualMachine<superscalar>::precompileSuperscalar(LightProgram* programs) {
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memcpy(superScalarPrograms, programs, sizeof(superScalarPrograms));
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reciprocals.clear();
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for (unsigned i = 0; i < RANDOMX_CACHE_ACCESSES; ++i) {
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for (unsigned j = 0; j < superScalarPrograms[i].getSize(); ++j) {
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Instruction& instr = superScalarPrograms[i](j);
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if (instr.opcode == LightInstructionType::IMUL_RCP) {
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auto rcp = reciprocal(instr.getImm32());
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instr.setImm32(reciprocals.size());
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reciprocals.push_back(rcp);
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}
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}
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}
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}
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#include "instructionWeights.hpp"
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void InterpretedVirtualMachine::precompileProgram(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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template<bool superscalar>
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void InterpretedVirtualMachine<superscalar>::precompileProgram(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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int registerUsage[8];
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for (unsigned i = 0; i < 8; ++i) {
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registerUsage[i] = -1;
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@@ -445,14 +575,17 @@ namespace RandomX {
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CASE_REP(IADD_RS) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IADD_R;
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ibc.type = InstructionType::IADD_RS;
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ibc.idst = &r[dst];
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if (src != dst) {
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if (dst != 5) {
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ibc.isrc = &r[src];
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ibc.shift = instr.mod % 4;
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ibc.imm = 0;
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}
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else {
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ibc.isrc = &r[src];
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ibc.shift = instr.mod % 4;
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ibc.imm = signExtend2sCompl(instr.getImm32());
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ibc.isrc = &ibc.imm;
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}
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registerUsage[instr.dst] = i;
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} break;
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