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120 Commits 8 Branches 5 Tags
88cf9d07285fa73816fe790a21fbe2784752b49f
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6 Commits

Author SHA1 Message Date
tevador
20eb549725 Merged load/store of integer and FP registers 2019-01-27 19:33:55 +01:00
tevador
005c67f64c Added explicit STORE instructions 
JIT compiler
 2019-01-27 10:52:30 +01:00
tevador
a7ffe8c19a Mix dataset cacheline with registers r0-r7 2019-01-13 21:14:59 +01:00
tevador
67e741ff22 Reduced x86 code size by 512 bytes (and ecx -> and eax) 2019-01-12 20:27:35 +01:00
tevador
d1a808643d Random accesses - JIT compiler 2019-01-10 22:04:55 +01:00
tevador
3caecc7646 Vector FPU instructions 
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
 2018-12-31 19:06:45 +01:00