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85 Commits 8 Branches 5 Tags
32d827d0a63c66f13cade760aeb0894e4868ee26
Commit Graph

7 Commits

Author SHA1 Message Date
tevador
32d827d0a6 Interpreter with bytecode 
Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
 2019-02-09 15:45:26 +01:00
tevador
a586751f6b Removed FPNEG instruction 
Optimized instruction frequencies
Increased the range for A registers from [1,65536) to [1, 4294967296)
 2019-02-07 16:11:27 +01:00
tevador
20eb549725 Merged load/store of integer and FP registers 2019-01-27 19:33:55 +01:00
tevador
005c67f64c Added explicit STORE instructions 
JIT compiler
 2019-01-27 10:52:30 +01:00
tevador
bd0dba88a8 4 scratchpad segments 2019-01-20 00:44:01 +01:00
tevador
d1a808643d Random accesses - JIT compiler 2019-01-10 22:04:55 +01:00
tevador
3caecc7646 Vector FPU instructions 
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
 2018-12-31 19:06:45 +01:00