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COND_R instruction reworked as CBRANCH

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instruction mod field bits reallocated
This commit is contained in:
tevador
2019-04-29 23:38:23 +02:00
parent ebddaf671c
commit ffebc37381
12 changed files with 166 additions and 313 deletions
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59
src/assembly_generator_x86.cpp
View File

@@ -44,14 +44,12 @@ namespace randomx {
static const char* regScratchpadAddr = "rsi";
void AssemblyGeneratorX86::generateProgram(Program& prog) {
for (unsigned i = 0; i < 8; ++i) {
for (unsigned i = 0; i < RegistersCount; ++i) {
registerUsage[i] = -1;
}
asmCode.str(std::string()); //clear
for (unsigned i = 0; i < prog.getSize(); ++i) {
#if RANDOMX_JUMP
asmCode << "randomx_isn_" << i << ":" << std::endl;
#endif
Instruction& instr = prog(i);
instr.src %= RegistersCount;
instr.dst %= RegistersCount;
@@ -261,7 +259,7 @@ namespace randomx {
void AssemblyGeneratorX86::genAddressRegDst(Instruction& instr, int maskAlign = 8) {
asmCode << "\tlea eax, [" << regR32[instr.dst] << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
int mask;
if (instr.getModCond()) {
if (instr.getModCond() < StoreL3Condition) {
mask = instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask;
}
else {
@@ -277,9 +275,9 @@ namespace randomx {
void AssemblyGeneratorX86::h_IADD_RS(Instruction& instr, int i) {
registerUsage[instr.dst] = i;
if(instr.dst == RegisterNeedsDisplacement)
asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModMem())) << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift())) << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
else
asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModMem())) << "]" << std::endl;
asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift())) << "]" << std::endl;
traceint(instr);
}
@@ -542,55 +540,18 @@ namespace randomx {
tracenop(instr);
}
static inline const char* condition(Instruction& instr) {
switch (instr.getModCond())
{
case 0:
return "be";
case 1:
return "a";
case 2:
return "s";
case 3:
return "ns";
case 4:
return "o";
case 5:
return "no";
case 6:
return "l";
case 7:
return "ge";
default:
UNREACHABLE;
}
}
void AssemblyGeneratorX86::handleCondition(Instruction& instr, int i) {
const int shift = instr.getModShift();
const int conditionMask = ((1 << RANDOMX_JUMP_BITS) - 1) << shift;
void AssemblyGeneratorX86::h_CBRANCH(Instruction& instr, int i) {
int reg = getConditionRegister();
int target = registerUsage[reg] + 1;
registerUsage[reg] = i;
asmCode << "\tadd " << regR[reg] << ", " << (1 << shift) << std::endl;
asmCode << "\ttest " << regR[reg] << ", " << conditionMask << std::endl;
int shift = instr.getModCond();
asmCode << "\tadd " << regR[reg] << ", " << (int32_t)(instr.getImm32() | (1 << shift)) << std::endl;
asmCode << "\ttest " << regR[reg] << ", " << (ConditionMask << shift) << std::endl;
asmCode << "\tjz randomx_isn_" << target << std::endl;
for (unsigned j = 0; j < 8; ++j) { //mark all registers as used
for (unsigned j = 0; j < RegistersCount; ++j) { //mark all registers as used
registerUsage[j] = i;
}
}
void AssemblyGeneratorX86::h_COND_R(Instruction& instr, int i) {
#if RANDOMX_JUMP
handleCondition(instr, i);
#endif
asmCode << "\txor ecx, ecx" << std::endl;
asmCode << "\tcmp " << regR32[instr.src] << ", " << (int32_t)instr.getImm32() << std::endl;
asmCode << "\tset" << condition(instr) << " cl" << std::endl;
asmCode << "\tadd " << regR[instr.dst] << ", rcx" << std::endl;
traceint(instr);
}
void AssemblyGeneratorX86::h_ISTORE(Instruction& instr, int i) {
genAddressRegDst(instr);
asmCode << "\tmov qword ptr [" << regScratchpadAddr << "+rax], " << regR[instr.src] << std::endl;
@@ -632,7 +593,7 @@ namespace randomx {
INST_HANDLE(FMUL_R)
INST_HANDLE(FDIV_M)
INST_HANDLE(FSQRT_R)
INST_HANDLE(COND_R)
INST_HANDLE(CBRANCH)
INST_HANDLE(CFROUND)
INST_HANDLE(ISTORE)
INST_HANDLE(NOP)

3
src/assembly_generator_x86.hpp
View File

@@ -44,7 +44,6 @@ namespace randomx {
void genAddressRegDst(Instruction&, int);
int32_t genAddressImm(Instruction&);
int getConditionRegister();
void handleCondition(Instruction&, int);
void generateCode(Instruction&, int);
void traceint(Instruction&);
void traceflt(Instruction&);
@@ -76,7 +75,7 @@ namespace randomx {
void h_FMUL_R(Instruction&, int);
void h_FDIV_M(Instruction&, int);
void h_FSQRT_R(Instruction&, int);
void h_COND_R(Instruction&, int);
void h_CBRANCH(Instruction&, int);
void h_CFROUND(Instruction&, int);
void h_ISTORE(Instruction&, int);
void h_NOP(Instruction&, int);

7
src/common.hpp
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@@ -40,13 +40,14 @@ namespace randomx {
static_assert(RANDOMX_SCRATCHPAD_L2 >= RANDOMX_SCRATCHPAD_L1, "RANDOMX_SCRATCHPAD_L2 must be greater than or equal to RANDOMX_SCRATCHPAD_L1.");
static_assert((RANDOMX_SCRATCHPAD_L1 & (RANDOMX_SCRATCHPAD_L1 - 1)) == 0, "RANDOMX_SCRATCHPAD_L1 must be a power of 2.");
static_assert(RANDOMX_CACHE_ACCESSES > 1, "RANDOMX_CACHE_ACCESSES must be greater than 1");
static_assert(RANDOMX_JUMP_BITS >= 1 && RANDOMX_JUMP_BITS <= 16, "RANDOMX_JUMP_BITS must be an integer in the range 1-16.");
constexpr int wtSum = RANDOMX_FREQ_IADD_RS + RANDOMX_FREQ_IADD_M + RANDOMX_FREQ_ISUB_R + \
RANDOMX_FREQ_ISUB_M + RANDOMX_FREQ_IMUL_R + RANDOMX_FREQ_IMUL_M + RANDOMX_FREQ_IMULH_R + \
RANDOMX_FREQ_IMULH_M + RANDOMX_FREQ_ISMULH_R + RANDOMX_FREQ_ISMULH_M + RANDOMX_FREQ_IMUL_RCP + \
RANDOMX_FREQ_INEG_R + RANDOMX_FREQ_IXOR_R + RANDOMX_FREQ_IXOR_M + RANDOMX_FREQ_IROR_R + RANDOMX_FREQ_ISWAP_R + \
RANDOMX_FREQ_FSWAP_R + RANDOMX_FREQ_FADD_R + RANDOMX_FREQ_FADD_M + RANDOMX_FREQ_FSUB_R + RANDOMX_FREQ_FSUB_M + \
RANDOMX_FREQ_FSCAL_R + RANDOMX_FREQ_FMUL_R + RANDOMX_FREQ_FDIV_M + RANDOMX_FREQ_FSQRT_R + RANDOMX_FREQ_COND_R + \
RANDOMX_FREQ_FSCAL_R + RANDOMX_FREQ_FMUL_R + RANDOMX_FREQ_FDIV_M + RANDOMX_FREQ_FSQRT_R + RANDOMX_FREQ_CBRANCH + \
RANDOMX_FREQ_CFROUND + RANDOMX_FREQ_ISTORE + RANDOMX_FREQ_NOP;
static_assert(wtSum == 256, "Sum of instruction frequencies must be 256.");
@@ -59,6 +60,8 @@ namespace randomx {
constexpr uint32_t CacheSize = RANDOMX_ARGON_MEMORY * ArgonBlockSize;
constexpr uint64_t DatasetSize = RANDOMX_DATASET_BASE_SIZE + RANDOMX_DATASET_EXTRA_SIZE;
constexpr uint32_t DatasetExtraItems = RANDOMX_DATASET_EXTRA_SIZE / RANDOMX_DATASET_ITEM_SIZE;
constexpr uint32_t ConditionMask = ((1 << RANDOMX_JUMP_BITS) - 1);
constexpr int StoreL3Condition = 14;
#ifdef TRACE
constexpr bool trace = true;
@@ -76,8 +79,6 @@ namespace randomx {
#endif
#endif
#define RANDOMX_JUMP (RANDOMX_JUMP_BITS > 0)
using addr_t = uint32_t;
using int_reg_t = uint64_t;

5
src/configuration.h
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@@ -64,7 +64,7 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
//Scratchpad L1 size in bytes. Must be a power of two and less than or equal to RANDOMX_SCRATCHPAD_L2.
#define RANDOMX_SCRATCHPAD_L1 (16 * 1024)
//How many register bits must be zero for a jump condition to be triggered. If set to 0, jumps are disabled.
//How many register bits must be zero for CBRANCH instruction to jump. Must be an integer in the range 1-16.
#define RANDOMX_JUMP_BITS 7
/*
@@ -100,8 +100,9 @@ Total sum of frequencies must be 256
#define RANDOMX_FREQ_FDIV_M 4
#define RANDOMX_FREQ_FSQRT_R 6
#define RANDOMX_FREQ_COND_R 8
#define RANDOMX_FREQ_CBRANCH 8
#define RANDOMX_FREQ_CFROUND 1
#define RANDOMX_FREQ_ISTORE 16
#define RANDOMX_FREQ_NOP 0

12
src/instruction.cpp
View File

@@ -33,7 +33,7 @@ namespace randomx {
}
void Instruction::genAddressRegDst(std::ostream& os) const {
if (getModCond())
if (getModCond() < StoreL3Condition)
os << (getModMem() ? "L1" : "L2");
else
os << "L3";
@@ -49,7 +49,7 @@ namespace randomx {
if(dst == RegisterNeedsDisplacement) {
os << ", " << (int32_t)getImm32();
}
os << ", LSH " << (int)getModMem() << std::endl;
os << ", SHFT " << (int)getModShift() << std::endl;
}
void Instruction::h_IADD_M(std::ostream& os) const {
@@ -278,8 +278,8 @@ namespace randomx {
}
}
void Instruction::h_COND_R(std::ostream& os) const {
os << "r" << (int)dst << ", " << condition(getModCond()) << "(r" << (int)src << ", " << (int32_t)getImm32() << "), LSH " << (int)(getModShift()) << std::endl;
void Instruction::h_CBRANCH(std::ostream& os) const {
os << (int32_t)getImm32() << ", COND " << (int)(getModCond()) << std::endl;
}
void Instruction::h_ISTORE(std::ostream& os) const {
@@ -321,7 +321,7 @@ namespace randomx {
INST_NAME(FMUL_R)
INST_NAME(FDIV_M)
INST_NAME(FSQRT_R)
INST_NAME(COND_R)
INST_NAME(CBRANCH)
INST_NAME(CFROUND)
INST_NAME(ISTORE)
INST_NAME(NOP)
@@ -354,7 +354,7 @@ namespace randomx {
INST_HANDLE(FMUL_R)
INST_HANDLE(FDIV_M)
INST_HANDLE(FSQRT_R)
INST_HANDLE(COND_R)
INST_HANDLE(CBRANCH)
INST_HANDLE(CFROUND)
INST_HANDLE(ISTORE)
INST_HANDLE(NOP)

12
src/instruction.hpp
View File

@@ -57,7 +57,7 @@ namespace randomx {
constexpr int FMUL_R = 23;
constexpr int FDIV_M = 24;
constexpr int FSQRT_R = 25;
constexpr int COND_R = 26;
constexpr int CBRANCH = 26;
constexpr int CFROUND = 27;
constexpr int ISTORE = 28;
constexpr int NOP = 29;
@@ -81,11 +81,11 @@ namespace randomx {
int getModMem() const {
return mod % 4; //bits 0-1
}
int getModCond() const {
return (mod >> 2) % 8; //bits 2-4
}
int getModShift() const {
return mod >> 5; //bits 5-7
return (mod >> 2) % 4; //bits 2-3
}
int getModCond() const {
return mod >> 4; //bits 4-7
}
void setMod(uint8_t val) {
mod = val;
@@ -129,7 +129,7 @@ namespace randomx {
void h_FMUL_R(std::ostream&) const;
void h_FDIV_M(std::ostream&) const;
void h_FSQRT_R(std::ostream&) const;
void h_COND_R(std::ostream&) const;
void h_CBRANCH(std::ostream&) const;
void h_CFROUND(std::ostream&) const;
void h_ISTORE(std::ostream&) const;
void h_NOP(std::ostream&) const;

85
src/jit_compiler_x86.cpp
View File

@@ -297,12 +297,10 @@ namespace randomx {
}
void JitCompilerX86::generateProgramPrologue(Program& prog, ProgramConfiguration& pcfg) {
#if RANDOMX_JUMP
instructionOffsets.clear();
for (unsigned i = 0; i < 8; ++i) {
registerUsage[i] = -1;
}
#endif
codePos = prologueSize;
memcpy(code + codePos - 48, &pcfg.eMask, sizeof(pcfg.eMask));
emit(REX_XOR_RAX_R64);
@@ -334,9 +332,7 @@ namespace randomx {
}
void JitCompilerX86::generateCode(Instruction& instr, int i) {
#if RANDOMX_JUMP
instructionOffsets.push_back(codePos);
#endif
auto generator = engine[instr.opcode];
(this->*generator)(instr, i);
}
@@ -457,7 +453,7 @@ namespace randomx {
}
emit32(instr.getImm32());
emitByte(AND_EAX_I);
if (instr.getModCond()) {
if (instr.getModCond() < StoreL3Condition) {
int32_t maskL1 = align16 ? ScratchpadL1Mask16 : ScratchpadL1Mask;
int32_t maskL2 = align16 ? ScratchpadL2Mask16 : ScratchpadL2Mask;
emit32(instr.getModMem() ? maskL1 : maskL2);
@@ -478,7 +474,7 @@ namespace randomx {
emitByte(0xac);
else
emitByte(0x04 + 8 * instr.dst);
genSIB(instr.getModMem(), instr.src, instr.dst);
genSIB(instr.getModShift(), instr.src, instr.dst);
if (instr.dst == RegisterNeedsDisplacement)
emit32(instr.getImm32());
}
@@ -774,56 +770,10 @@ namespace randomx {
emit(AND_OR_MOV_LDMXCSR);
}
static inline uint8_t jumpCondition(Instruction& instr, bool invert = false) {
switch (instr.getModCond() ^ invert)
{
case 0:
return 0x76; //jbe
case 1:
return 0x77; //ja
case 2:
return 0x78; //js
case 3:
return 0x79; //jns
case 4:
return 0x70; //jo
case 5:
return 0x71; //jno
case 6:
return 0x7c; //jl
case 7:
return 0x7d; //jge
}
}
static inline uint8_t condition(Instruction& instr) {
switch (instr.getModCond())
{
case 0:
return 0x96; //setbe
case 1:
return 0x97; //seta
case 2:
return 0x98; //sets
case 3:
return 0x99; //setns
case 4:
return 0x90; //seto
case 5:
return 0x91; //setno
case 6:
return 0x9c; //setl
case 7:
return 0x9d; //setge
default:
UNREACHABLE;
}
}
int JitCompilerX86::getConditionRegister() {
int min = INT_MAX;
int minIndex;
for (unsigned i = 0; i < 8; ++i) {
for (unsigned i = 0; i < RegistersCount; ++i) {
if (registerUsage[i] < min) {
min = registerUsage[i];
minIndex = i;
@@ -832,40 +782,23 @@ namespace randomx {
return minIndex;
}
void JitCompilerX86::handleCondition(Instruction& instr, int i) {
const int shift = instr.getModShift();
const int conditionMask = ((1 << RANDOMX_JUMP_BITS) - 1) << shift;
void JitCompilerX86::h_CBRANCH(Instruction& instr, int i) {
int reg = getConditionRegister();
int target = registerUsage[reg] + 1;
int shift = instr.getModCond();
emit(REX_ADD_I);
emitByte(0xc0 + reg);
emit32(1 << shift);
emit32(instr.getImm32() | (1 << shift));
emit(REX_TEST);
emitByte(0xc0 + reg);
emit32(conditionMask);
emit32(ConditionMask << shift);
emit(JZ);
emit32(instructionOffsets[target] - (codePos + 4));
for (unsigned j = 0; j < 8; ++j) { //mark all registers as used
for (unsigned j = 0; j < RegistersCount; ++j) { //mark all registers as used
registerUsage[j] = i;
}
}
void JitCompilerX86::h_COND_R(Instruction& instr, int i) {
#if RANDOMX_JUMP
handleCondition(instr, i);
#endif
emit(XOR_ECX_ECX);
emit(REX_CMP_R32I);
emitByte(0xf8 + instr.src);
emit32(instr.getImm32());
emitByte(0x0f);
emitByte(condition(instr));
emitByte(0xc1);
emit(REX_ADD_RM);
emitByte(0xc1 + 8 * instr.dst);
}
void JitCompilerX86::h_ISTORE(Instruction& instr, int i) {
genAddressRegDst(instr);
emit(REX_MOV_MR);
@@ -907,7 +840,7 @@ namespace randomx {
INST_HANDLE(FMUL_R)
INST_HANDLE(FDIV_M)
INST_HANDLE(FSQRT_R)
INST_HANDLE(COND_R)
INST_HANDLE(CBRANCH)
INST_HANDLE(CFROUND)
INST_HANDLE(ISTORE)
INST_HANDLE(NOP)

4
src/jit_compiler_x86.hpp
View File

@@ -70,8 +70,6 @@ namespace randomx {
void genAddressImm(Instruction&);
void genSIB(int scale, int index, int base);
void handleCondition(Instruction&, int);
void generateCode(Instruction&, int);
void generateSuperscalarCode(Instruction &, std::vector<uint64_t> &);
@@ -136,7 +134,7 @@ namespace randomx {
void h_FMUL_R(Instruction&, int);
void h_FDIV_M(Instruction&, int);
void h_FSQRT_R(Instruction&, int);
void h_COND_R(Instruction&, int);
void h_CBRANCH(Instruction&, int);
void h_CFROUND(Instruction&, int);
void h_ISTORE(Instruction&, int);
void h_NOP(Instruction&, int);

2
src/tests/benchmark.cpp
View File

@@ -229,7 +229,7 @@ int main(int argc, char** argv) {
std::cout << "Calculated result: ";
result.print(std::cout);
if (noncesCount == 1000 && seedValue == 0)
std::cout << "Reference result: 89336a85bf6d1e83eb20fbc92170705ded9b42285b30178ed8e855d65c4c4b69" << std::endl;
std::cout << "Reference result: 804fed4a3dc4ed12917a210aad295925544e688e28549d7178eb27f412476a10" << std::endl;
if (!miningMode) {
std::cout << "Performance: " << 1000 * elapsed / noncesCount << " ms per hash" << std::endl;
}

34
src/vm_interpreted.cpp
View File

@@ -180,16 +180,11 @@ namespace randomx {
*ibc.fdst = _mm_sqrt_pd(*ibc.fdst);
} break;
case InstructionType::COND_R: {
#if RANDOMX_JUMP
*ibc.creg += (1 << ibc.shift);
const uint64_t conditionMask = ((1ULL << RANDOMX_JUMP_BITS) - 1) << ibc.shift;
if ((*ibc.creg & conditionMask) == 0) {
case InstructionType::CBRANCH: {
*ibc.isrc += ibc.imm;
if ((*ibc.isrc & ibc.memMask) == 0) {
pc = ibc.target;
break;
}
#endif
*ibc.idst += condition(ibc.condition, *ibc.isrc, ibc.imm) ? 1 : 0;
} break;
case InstructionType::CFROUND: {
@@ -308,12 +303,12 @@ namespace randomx {
ibc.idst = &r[dst];
if (dst != RegisterNeedsDisplacement) {
ibc.isrc = &r[src];
ibc.shift = instr.getModMem();
ibc.shift = instr.getModShift();
ibc.imm = 0;
}
else {
ibc.isrc = &r[src];
ibc.shift = instr.getModMem();
ibc.shift = instr.getModShift();
ibc.imm = signExtend2sCompl(instr.getImm32());
}
registerUsage[dst] = i;
@@ -626,19 +621,16 @@ namespace randomx {
ibc.fdst = &e[dst];
} break;
CASE_REP(COND_R) {
auto dst = instr.dst % RegistersCount;
auto src = instr.src % RegistersCount;
ibc.type = InstructionType::COND_R;
ibc.idst = &r[dst];
ibc.isrc = &r[src];
ibc.condition = instr.getModCond();
ibc.imm = instr.getImm32();
CASE_REP(CBRANCH) {
ibc.type = InstructionType::CBRANCH;
//jump condition
int reg = getConditionRegister(registerUsage);
ibc.isrc = &r[reg];
ibc.target = registerUsage[reg];
ibc.shift = instr.getModShift();
ibc.creg = &r[reg];
int shift = instr.getModCond();
const uint64_t conditionMask = ConditionMask << instr.getModCond();
ibc.imm = signExtend2sCompl(instr.getImm32()) | (1ULL << shift);
ibc.memMask = ConditionMask << shift;
for (unsigned j = 0; j < RegistersCount; ++j) { //mark all registers as used
registerUsage[j] = i;
}
@@ -658,7 +650,7 @@ namespace randomx {
ibc.idst = &r[dst];
ibc.isrc = &r[src];
ibc.imm = signExtend2sCompl(instr.getImm32());
if (instr.getModCond())
if (instr.getModCond() < StoreL3Condition)
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
else
ibc.memMask = ScratchpadL3Mask;

10
src/vm_interpreted.hpp
View File

@@ -41,12 +41,12 @@ namespace randomx {
uint64_t imm;
int64_t simm;
};
int_reg_t* creg;
uint16_t condition;
int16_t target;
uint32_t memMask;
uint16_t type;
uint16_t shift;
union {
int16_t target;
uint16_t shift;
};
uint32_t memMask;
};
template<class Allocator, bool softAes>