mirror of
https://codeberg.org/wownero/RandomWOW
synced 2026-03-05 14:17:33 -05:00
ASM code generator for "small" programs that fit into the uOP cache
This commit is contained in:
tevador
@@ -30,12 +30,20 @@ namespace RandomX {
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static const char* regR[8] = { "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" };
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static const char* regR32[8] = { "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" };
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static const char* regF[8] = { "xmm8", "xmm9", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" };
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static const char* regFE[8] = { "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" };
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static const char* regF[4] = { "xmm0", "xmm1", "xmm2", "xmm3" };
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static const char* regE[4] = { "xmm4", "xmm5", "xmm6", "xmm7" };
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static const char* regA[4] = { "xmm8", "xmm9", "xmm10", "xmm11" };
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static const char* regA4 = "xmm12";
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static const char* dblMin = "xmm13";
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static const char* absMask = "xmm14";
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static const char* signMask = "xmm15";
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static const char* regMx = "rbp";
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static const char* regIc = "ebx";
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static const char* regIc = "rbx";
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static const char* regIc32 = "ebx";
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static const char* regIc8 = "bl";
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static const char* regStackBeginAddr = "rdi";
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static const char* regDatasetAddr = "rdi";
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static const char* regScratchpadAddr = "rsi";
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void AssemblyGeneratorX86::generateProgram(const void* seed) {
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@@ -49,226 +57,217 @@ namespace RandomX {
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for (unsigned j = 0; j < sizeof(instr) / sizeof(Pcg32::result_type); ++j) {
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*(((uint32_t*)&instr) + j) = gen();
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}
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instr.src %= RegistersCount;
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instr.dst %= RegistersCount;
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generateCode(instr, i);
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asmCode << std::endl;
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//asmCode << std::endl;
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}
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if(ProgramLength > 0)
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asmCode << "\tjmp rx_i_0" << std::endl;
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}
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void AssemblyGeneratorX86::generateCode(Instruction& instr, int i) {
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asmCode << "rx_i_" << i << ": ;" << instr.getName() << std::endl;
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asmCode << "\tdec " << regIc << std::endl;
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asmCode << "\tjz rx_finish" << std::endl;
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asmCode << "\t; " << instr;
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auto generator = engine[instr.opcode];
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(this->*generator)(instr, i);
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}
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void AssemblyGeneratorX86::gena(Instruction& instr, int i) {
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asmCode << "\txor " << regR[instr.rega % RegistersCount] << ", 0" << std::hex << instr.addra << "h" << std::dec << std::endl;
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asmCode << "\tmov eax, " << regR32[instr.rega % RegistersCount] << std::endl;
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asmCode << "\ttest " << regIc8 << ", 63" << std::endl;
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asmCode << "\tjnz short rx_body_" << i << std::endl;
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asmCode << "\tcall rx_read" << std::endl;
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asmCode << "rx_body_" << i << ":" << std::endl;
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if ((instr.loca & 192) == 0)
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asmCode << "\txor " << regMx << ", rax" << std::endl;
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if (instr.loca & 15) {
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if (instr.loca & 3) {
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asmCode << "\tand eax, " << (ScratchpadL1 - 1) << std::endl;
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}
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else {
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asmCode << "\tand eax, " << (ScratchpadL2 - 1) << std::endl;
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}
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void AssemblyGeneratorX86::genAddressReg(Instruction& instr, const char* reg = "eax") {
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asmCode << "\tmov " << reg << ", " << regR32[instr.src] << std::endl;
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asmCode << "\tand " << reg << ", " << ((instr.alt % 4) ? ScratchpadL1Mask : ScratchpadL2Mask) << std::endl;
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}
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int32_t AssemblyGeneratorX86::genAddressImm(Instruction& instr) {
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return instr.imm32 & ((instr.alt % 4) ? ScratchpadL1Mask : ScratchpadL2Mask);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IADD_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\tadd " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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else {
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asmCode << "\tand eax, " << (ScratchpadL3 - 1) << std::endl;
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asmCode << "\tadd " << regR[instr.dst] << ", " << instr.imm32 << std::endl;
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}
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}
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void AssemblyGeneratorX86::genar(Instruction& instr, int i) {
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gena(instr, i);
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asmCode << "\tmov rax, qword ptr [" << regScratchpadAddr << "+rax*8]" << std::endl;
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}
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void AssemblyGeneratorX86::genaf(Instruction& instr, int i) {
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gena(instr, i);
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asmCode << "\tcvtdq2pd xmm0, qword ptr [" << regScratchpadAddr << "+rax*8]" << std::endl;
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}
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void AssemblyGeneratorX86::genbiashift(Instruction& instr, const char* instrx86) {
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if (instr.locb & 1) {
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asmCode << "\tmov rcx, " << regR[instr.regb % RegistersCount] << std::endl;
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asmCode << "\t" << instrx86 << " rax, cl" << std::endl;
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} else {
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asmCode << "\t" << instrx86 << " rax, " << (instr.imm8 & 63) << std::endl;;
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}
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}
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void AssemblyGeneratorX86::genbia(Instruction& instr) {
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if (instr.locb & 3) {
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asmCode << regR[instr.regb % RegistersCount] << std::endl;
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} else {
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asmCode << instr.imm32 << std::endl;;
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}
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}
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void AssemblyGeneratorX86::genbia32(Instruction& instr) {
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if (instr.locb & 3) {
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asmCode << regR32[instr.regb % RegistersCount] << std::endl;
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//2.75 uOP
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void AssemblyGeneratorX86::h_IADD_M(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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}
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else {
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asmCode << instr.imm32 << std::endl;;
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asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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}
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void AssemblyGeneratorX86::genbf(Instruction& instr, const char* instrx86) {
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asmCode << "\t" << instrx86 << " xmm0, " << regF[instr.regb % RegistersCount] << std::endl;
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//1 uOP
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void AssemblyGeneratorX86::h_IADD_RC(Instruction& instr, int i) {
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << std::showpos << instr.imm32 << std::noshowpos << "]" << std::endl;
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}
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void AssemblyGeneratorX86::gencr(Instruction& instr, bool rax = true) {
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if (instr.locc & 16) { //write to register
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asmCode << "\tmov " << regR[instr.regc % RegistersCount] << ", " << (rax ? "rax" : "rcx") << std::endl;
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if (trace) {
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asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + " << regIc << " * 8 + 262136], " << (rax ? "rax" : "rcx") << std::endl;
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}
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//1 uOP
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void AssemblyGeneratorX86::h_ISUB_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\tsub " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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else { //write to scratchpad
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if (rax)
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asmCode << "\tmov rcx, rax" << std::endl;
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asmCode << "\tmov eax, " << regR32[instr.regc % RegistersCount] << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addrc << "h" << std::dec << std::endl;
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if (instr.locc & 15) {
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if (instr.locc & 3) {
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asmCode << "\tand eax, " << (ScratchpadL1 - 1) << std::endl;
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}
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else {
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asmCode << "\tand eax, " << (ScratchpadL2 - 1) << std::endl;
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}
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}
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else {
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asmCode << "\tand eax, " << (ScratchpadL3 - 1) << std::endl;
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}
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asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + rax * 8], rcx" << std::endl;
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if (trace) {
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asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + " << regIc << " * 8 + 262136], rcx" << std::endl;
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}
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else {
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asmCode << "\tsub " << regR[instr.dst] << ", " << instr.imm32 << std::endl;
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}
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}
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void AssemblyGeneratorX86::gencf(Instruction& instr, bool move = true) {
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if(move)
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asmCode << "\tmovaps " << regF[instr.regc % RegistersCount] << ", xmm0" << std::endl;
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const char* store = (instr.locc & 128) ? "movhpd" : "movlpd";
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if (instr.locc & 16) { //write to scratchpad
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asmCode << "\tmov eax, " << regR32[instr.regc % RegistersCount] << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addrc << "h" << std::dec << std::endl;
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if (instr.locc & 15) {
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if (instr.locc & 3) {
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asmCode << "\tand eax, " << (ScratchpadL1 - 1) << std::endl;
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}
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else {
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asmCode << "\tand eax, " << (ScratchpadL2 - 1) << std::endl;
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}
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}
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else {
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asmCode << "\tand eax, " << (ScratchpadL3 - 1) << std::endl;
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}
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asmCode << "\t" << store << " qword ptr [" << regScratchpadAddr << " + rax * 8], " << regF[instr.regc % RegistersCount] << std::endl;
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//2.75 uOP
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void AssemblyGeneratorX86::h_ISUB_M(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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}
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if (trace) {
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asmCode << "\t" << store << " qword ptr [" << regScratchpadAddr << " + " << regIc << " * 8 + 262136], " << regF[instr.regc % RegistersCount] << std::endl;
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else {
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asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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}
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void AssemblyGeneratorX86::h_ADD_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tadd rax, ";
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genbia(instr);
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gencr(instr);
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//1 uOP
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void AssemblyGeneratorX86::h_IMUL_9C(Instruction& instr, int i) {
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.dst] << "*8" << std::showpos << instr.imm32 << std::noshowpos << "]" << std::endl;
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}
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void AssemblyGeneratorX86::h_ADD_32(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tadd eax, ";
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genbia32(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_SUB_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tsub rax, ";
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genbia(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_SUB_32(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tsub eax, ";
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genbia32(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_MUL_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\timul rax, ";
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if ((instr.locb & 3) == 0) {
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asmCode << "rax, ";
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//1 uOP
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void AssemblyGeneratorX86::h_IMUL_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\timul " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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else {
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asmCode << "\timul " << regR[instr.dst] << ", " << instr.imm32 << std::endl;
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}
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genbia(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_MULH_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tmov rcx, ";
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genbia(instr);
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asmCode << "\tmul rcx" << std::endl;
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asmCode << "\tmov rax, rdx" << std::endl;
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gencr(instr);
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//2.75 uOP
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void AssemblyGeneratorX86::h_IMUL_M(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\timul " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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}
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else {
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asmCode << "\timul " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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}
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void AssemblyGeneratorX86::h_MUL_32(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tmov ecx, eax" << std::endl;
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asmCode << "\tmov eax, ";
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genbia32(instr);
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asmCode << "\timul rax, rcx" << std::endl;
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gencr(instr);
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//4 uOPs
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void AssemblyGeneratorX86::h_IMULH_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\tmul " << regR[instr.src] << std::endl;
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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}
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else {
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asmCode << "\tmov eax, " << instr.imm32 << std::endl;
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asmCode << "\tmul " << regR[instr.dst] << std::endl;
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asmCode << "\tadd " << regR[instr.dst] << ", rdx" << std::endl;
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}
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}
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void AssemblyGeneratorX86::h_IMUL_32(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tmovsxd rcx, eax" << std::endl;
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if ((instr.locb & 3) == 0) {
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//5.75 uOPs
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void AssemblyGeneratorX86::h_IMULH_M(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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genAddressReg(instr, "ecx");
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\tmul qword ptr [rsi+rcx]" << std::endl;
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}
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else {
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\tmul qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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}
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//4 uOPs
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void AssemblyGeneratorX86::h_ISMULH_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\timul " << regR[instr.src] << std::endl;
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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}
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else {
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asmCode << "\tmov rax, " << instr.imm32 << std::endl;
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asmCode << "\timul " << regR[instr.dst] << std::endl;
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asmCode << "\tadd " << regR[instr.dst] << ", rdx" << std::endl;
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}
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}
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//5.75 uOPs
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void AssemblyGeneratorX86::h_ISMULH_M(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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genAddressReg(instr, "ecx");
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\timul qword ptr [rsi+rcx]" << std::endl;
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}
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else {
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asmCode << "\tmovsxd rax, " << regR32[instr.regb % RegistersCount] << std::endl;
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\timul qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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asmCode << "\timul rax, rcx" << std::endl;
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gencr(instr);
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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}
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void AssemblyGeneratorX86::h_IMULH_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tmov rcx, ";
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genbia(instr);
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asmCode << "\timul rcx" << std::endl;
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asmCode << "\tmov rax, rdx" << std::endl;
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gencr(instr);
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//1 uOP
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void AssemblyGeneratorX86::h_INEG_R(Instruction& instr, int i) {
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asmCode << "\tneg " << regR[instr.dst] << std::endl;
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}
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void AssemblyGeneratorX86::h_DIV_64(Instruction& instr, int i) {
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genar(instr, i);
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if (instr.locb & 3) {
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#ifdef MAGIC_DIVISION
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if (instr.imm32 != 0) {
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uint32_t divisor = instr.imm32;
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asmCode << "\t; magic divide by " << divisor << std::endl;
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if (divisor & (divisor - 1)) {
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magicu_info mi = compute_unsigned_magic_info(divisor, sizeof(uint64_t) * 8);
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//1 uOP
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void AssemblyGeneratorX86::h_IXOR_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\txor " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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else {
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asmCode << "\txor " << regR[instr.dst] << ", " << instr.imm32 << std::endl;
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}
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}
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//2.75 uOP
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void AssemblyGeneratorX86::h_IXOR_M(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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genAddressReg(instr);
|
||||
asmCode << "\txor " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
|
||||
}
|
||||
else {
|
||||
asmCode << "\txor " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
|
||||
}
|
||||
}
|
||||
|
||||
//1.75 uOPs
|
||||
void AssemblyGeneratorX86::h_IROR_R(Instruction& instr, int i) {
|
||||
if (instr.src != instr.dst) {
|
||||
asmCode << "\tmov ecx, " << regR32[instr.src] << std::endl;
|
||||
asmCode << "\tror " << regR[instr.dst] << ", cl" << std::endl;
|
||||
}
|
||||
else {
|
||||
asmCode << "\tror " << regR[instr.dst] << ", " << (instr.imm32 & 63) << std::endl;
|
||||
}
|
||||
}
|
||||
|
||||
//1.75 uOPs
|
||||
void AssemblyGeneratorX86::h_IROL_R(Instruction& instr, int i) {
|
||||
if (instr.src != instr.dst) {
|
||||
asmCode << "\tmov ecx, " << regR32[instr.src] << std::endl;
|
||||
asmCode << "\trol " << regR[instr.dst] << ", cl" << std::endl;
|
||||
}
|
||||
else {
|
||||
asmCode << "\trol " << regR[instr.dst] << ", " << (instr.imm32 & 63) << std::endl;
|
||||
}
|
||||
}
|
||||
|
||||
//~6 uOPs
|
||||
void AssemblyGeneratorX86::h_IDIV_C(Instruction& instr, int i) {
|
||||
if (instr.imm32 != 0) {
|
||||
uint32_t divisor = instr.imm32;
|
||||
if (divisor & (divisor - 1)) {
|
||||
magicu_info mi = compute_unsigned_magic_info(divisor, sizeof(uint64_t) * 8);
|
||||
if (mi.pre_shift == 0 && !mi.increment) {
|
||||
asmCode << "\tmov rax, " << mi.multiplier << std::endl;
|
||||
asmCode << "\tmul " << regR[instr.dst] << std::endl;
|
||||
}
|
||||
else {
|
||||
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
|
||||
if (mi.pre_shift > 0)
|
||||
asmCode << "\tshr rax, " << mi.pre_shift << std::endl;
|
||||
if (mi.increment) {
|
||||
@@ -277,326 +276,249 @@ namespace RandomX {
|
||||
}
|
||||
asmCode << "\tmov rcx, " << mi.multiplier << std::endl;
|
||||
asmCode << "\tmul rcx" << std::endl;
|
||||
asmCode << "\tmov rax, rdx" << std::endl;
|
||||
if (mi.post_shift > 0)
|
||||
asmCode << "\tshr rax, " << mi.post_shift << std::endl;
|
||||
}
|
||||
else { //divisor is a power of two
|
||||
int shift = 0;
|
||||
while (divisor >>= 1)
|
||||
++shift;
|
||||
if(shift > 0)
|
||||
asmCode << "\tshr rax, " << shift << std::endl;
|
||||
}
|
||||
if (mi.post_shift > 0)
|
||||
asmCode << "\tshr rdx, " << mi.post_shift << std::endl;
|
||||
asmCode << "\tadd " << regR[instr.dst] << ", rdx" << std::endl;
|
||||
}
|
||||
#else
|
||||
if (instr.imm32 == 0) {
|
||||
asmCode << "\tmov ecx, 1" << std::endl;
|
||||
}
|
||||
else {
|
||||
asmCode << "\tmov ecx, " << instr.imm32 << std::endl;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
asmCode << "\tmov ecx, 1" << std::endl;
|
||||
asmCode << "\tmov edx, " << regR32[instr.regb % RegistersCount] << std::endl;
|
||||
asmCode << "\ttest edx, edx" << std::endl;
|
||||
asmCode << "\tcmovne ecx, edx" << std::endl;
|
||||
#ifdef MAGIC_DIVISION
|
||||
asmCode << "\txor edx, edx" << std::endl;
|
||||
asmCode << "\tdiv rcx" << std::endl;
|
||||
#endif
|
||||
}
|
||||
#ifndef MAGIC_DIVISION
|
||||
asmCode << "\txor edx, edx" << std::endl;
|
||||
asmCode << "\tdiv rcx" << std::endl;
|
||||
#endif
|
||||
gencr(instr);
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_IDIV_64(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
if (instr.locb & 3) {
|
||||
#ifdef MAGIC_DIVISION
|
||||
int64_t divisor = instr.imm32;
|
||||
asmCode << "\t; magic divide by " << divisor << std::endl;
|
||||
if ((divisor & -divisor) == divisor || (divisor & -divisor) == -divisor) {
|
||||
// +/- power of two
|
||||
bool negative = divisor < 0;
|
||||
if (negative)
|
||||
divisor = -divisor;
|
||||
else { //divisor is a power of two
|
||||
int shift = 0;
|
||||
uint64_t unsignedDivisor = divisor;
|
||||
while (unsignedDivisor >>= 1)
|
||||
while (divisor >>= 1)
|
||||
++shift;
|
||||
if (shift > 0) {
|
||||
asmCode << "\tmov rcx, rax" << std::endl;
|
||||
asmCode << "\tsar rcx, 63" << std::endl;
|
||||
uint32_t mask = (1ULL << shift) + 0xFFFFFFFF;
|
||||
asmCode << "\tand ecx, 0" << std::hex << mask << std::dec << "h" << std::endl;
|
||||
asmCode << "\tadd rax, rcx" << std::endl;
|
||||
asmCode << "\tsar rax, " << shift << std::endl;
|
||||
}
|
||||
if (negative)
|
||||
asmCode << "\tneg rax" << std::endl;
|
||||
if(shift > 0)
|
||||
asmCode << "\tshr " << regR[instr.dst] << ", " << shift << std::endl;
|
||||
}
|
||||
else if (divisor != 0) {
|
||||
magics_info mi = compute_signed_magic_info(divisor);
|
||||
if ((divisor >= 0) != (mi.multiplier >= 0))
|
||||
asmCode << "\tmov rcx, rax" << std::endl;
|
||||
asmCode << "\tmov rdx, " << mi.multiplier << std::endl;
|
||||
asmCode << "\timul rdx" << std::endl;
|
||||
asmCode << "\tmov rax, rdx" << std::endl;
|
||||
asmCode << "\txor edx, edx" << std::endl;
|
||||
bool haveSF = false;
|
||||
if (divisor > 0 && mi.multiplier < 0) {
|
||||
asmCode << "\tadd rax, rcx" << std::endl;
|
||||
haveSF = true;
|
||||
}
|
||||
if (divisor < 0 && mi.multiplier > 0) {
|
||||
asmCode << "\tsub rax, rcx" << std::endl;
|
||||
haveSF = true;
|
||||
}
|
||||
if (mi.shift > 0) {
|
||||
asmCode << "\tsar rax, " << mi.shift << std::endl;
|
||||
haveSF = true;
|
||||
}
|
||||
if (!haveSF)
|
||||
asmCode << "\ttest rax, rax" << std::endl;
|
||||
asmCode << "\tsets dl" << std::endl;
|
||||
asmCode << "\tadd rax, rdx" << std::endl;
|
||||
}
|
||||
}
|
||||
|
||||
//~8.5 uOPs
|
||||
void AssemblyGeneratorX86::h_ISDIV_C(Instruction& instr, int i) {
|
||||
int64_t divisor = instr.imm32;
|
||||
if ((divisor & -divisor) == divisor || (divisor & -divisor) == -divisor) {
|
||||
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
|
||||
// +/- power of two
|
||||
bool negative = divisor < 0;
|
||||
if (negative)
|
||||
divisor = -divisor;
|
||||
int shift = 0;
|
||||
uint64_t unsignedDivisor = divisor;
|
||||
while (unsignedDivisor >>= 1)
|
||||
++shift;
|
||||
if (shift > 0) {
|
||||
asmCode << "\tmov rcx, rax" << std::endl;
|
||||
asmCode << "\tsar rcx, 63" << std::endl;
|
||||
uint32_t mask = (1ULL << shift) + 0xFFFFFFFF;
|
||||
asmCode << "\tand ecx, 0" << std::hex << mask << std::dec << "h" << std::endl;
|
||||
asmCode << "\tadd rax, rcx" << std::endl;
|
||||
asmCode << "\tsar rax, " << shift << std::endl;
|
||||
}
|
||||
#else
|
||||
asmCode << "\tmov edx, " << instr.imm32 << std::endl;
|
||||
#endif
|
||||
if (negative)
|
||||
asmCode << "\tneg rax" << std::endl;
|
||||
asmCode << "\tadd " << regR[instr.dst] << ", rax" << std::endl;
|
||||
}
|
||||
else {
|
||||
asmCode << "\tmov edx, " << regR32[instr.regb % RegistersCount] << std::endl;
|
||||
#ifndef MAGIC_DIVISION
|
||||
else if (divisor != 0) {
|
||||
magics_info mi = compute_signed_magic_info(divisor);
|
||||
asmCode << "\tmov rax, " << mi.multiplier << std::endl;
|
||||
asmCode << "\timul " << regR[instr.dst] << std::endl;
|
||||
//asmCode << "\tmov rax, rdx" << std::endl;
|
||||
asmCode << "\txor eax, eax" << std::endl;
|
||||
bool haveSF = false;
|
||||
if (divisor > 0 && mi.multiplier < 0) {
|
||||
asmCode << "\tadd rdx, " << regR[instr.dst] << std::endl;
|
||||
haveSF = true;
|
||||
}
|
||||
if (divisor < 0 && mi.multiplier > 0) {
|
||||
asmCode << "\tsub rdx, " << regR[instr.dst] << std::endl;
|
||||
haveSF = true;
|
||||
}
|
||||
if (mi.shift > 0) {
|
||||
asmCode << "\tsar rdx, " << mi.shift << std::endl;
|
||||
haveSF = true;
|
||||
}
|
||||
if (!haveSF)
|
||||
asmCode << "\ttest rdx, rdx" << std::endl;
|
||||
asmCode << "\tsets al" << std::endl;
|
||||
asmCode << "\tadd rdx, rax" << std::endl;
|
||||
asmCode << "\tadd " << regR[instr.dst] << ", rdx" << std::endl;
|
||||
}
|
||||
#endif
|
||||
asmCode << "\tcmp edx, -1" << std::endl;
|
||||
asmCode << "\tjne short body_idiv_" << i << std::endl;
|
||||
asmCode << "\tneg rax" << std::endl;
|
||||
asmCode << "\tjmp short result_idiv_" << i << std::endl;
|
||||
asmCode << "body_idiv_" << i << ":" << std::endl;
|
||||
asmCode << "\tmov ecx, 1" << std::endl;
|
||||
asmCode << "\ttest edx, edx" << std::endl;
|
||||
asmCode << "\tcmovne ecx, edx" << std::endl;
|
||||
asmCode << "\tmovsxd rcx, ecx" << std::endl;
|
||||
asmCode << "\tcqo" << std::endl;
|
||||
asmCode << "\tidiv rcx" << std::endl;
|
||||
asmCode << "result_idiv_" << i << ":" << std::endl;
|
||||
#ifdef MAGIC_DIVISION
|
||||
}
|
||||
#endif
|
||||
gencr(instr);
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_AND_64(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
asmCode << "\tand rax, ";
|
||||
genbia(instr);
|
||||
gencr(instr);
|
||||
//1 uOPs
|
||||
void AssemblyGeneratorX86::h_FPSWAP_R(Instruction& instr, int i) {
|
||||
asmCode << "\tshufpd " << regFE[instr.dst] << ", " << regFE[instr.dst] << ", 1" << std::endl;
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_AND_32(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
asmCode << "\tand eax, ";
|
||||
genbia32(instr);
|
||||
gencr(instr);
|
||||
//1 uOP
|
||||
void AssemblyGeneratorX86::h_FPADD_R(Instruction& instr, int i) {
|
||||
instr.dst %= 4;
|
||||
instr.src %= 4;
|
||||
asmCode << "\taddpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl;
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_OR_64(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
asmCode << "\tor rax, ";
|
||||
genbia(instr);
|
||||
gencr(instr);
|
||||
//5 uOPs
|
||||
void AssemblyGeneratorX86::h_FPADD_M(Instruction& instr, int i) {
|
||||
instr.dst %= 4;
|
||||
genAddressReg(instr);
|
||||
asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
|
||||
asmCode << "\taddpd " << regF[instr.dst] << ", xmm12" << std::endl;
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_OR_32(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
asmCode << "\tor eax, ";
|
||||
genbia32(instr);
|
||||
gencr(instr);
|
||||
//1 uOP
|
||||
void AssemblyGeneratorX86::h_FPSUB_R(Instruction& instr, int i) {
|
||||
instr.dst %= 4;
|
||||
instr.src %= 4;
|
||||
asmCode << "\tsubpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl;
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_XOR_64(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
asmCode << "\txor rax, ";
|
||||
genbia(instr);
|
||||
gencr(instr);
|
||||
//5 uOPs
|
||||
void AssemblyGeneratorX86::h_FPSUB_M(Instruction& instr, int i) {
|
||||
instr.dst %= 4;
|
||||
genAddressReg(instr);
|
||||
asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
|
||||
asmCode << "\tsubpd " << regF[instr.dst] << ", xmm12" << std::endl;
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_XOR_32(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
asmCode << "\txor eax, ";
|
||||
genbia32(instr);
|
||||
gencr(instr);
|
||||
//1 uOP
|
||||
void AssemblyGeneratorX86::h_FPNEG_R(Instruction& instr, int i) {
|
||||
instr.dst %= 4;
|
||||
asmCode << "\txorps " << regF[instr.dst] << ", " << signMask << std::endl;
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_SHL_64(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
genbiashift(instr, "shl");
|
||||
gencr(instr);
|
||||
//1 uOPs
|
||||
void AssemblyGeneratorX86::h_FPMUL_R(Instruction& instr, int i) {
|
||||
instr.dst %= 4;
|
||||
instr.src %= 4;
|
||||
asmCode << "\tmulpd " << regE[instr.dst] << ", " << regA[instr.src] << std::endl;
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_SHR_64(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
genbiashift(instr, "shr");
|
||||
gencr(instr);
|
||||
//6 uOPs
|
||||
void AssemblyGeneratorX86::h_FPMUL_M(Instruction& instr, int i) {
|
||||
instr.dst %= 4;
|
||||
genAddressReg(instr);
|
||||
asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
|
||||
asmCode << "\tmulpd " << regE[instr.dst] << ", xmm12" << std::endl;
|
||||
asmCode << "\tmaxpd " << regE[instr.dst] << ", " << dblMin << std::endl;
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_SAR_64(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
genbiashift(instr, "sar");
|
||||
gencr(instr);
|
||||
//2 uOPs
|
||||
void AssemblyGeneratorX86::h_FPDIV_R(Instruction& instr, int i) {
|
||||
instr.dst %= 4;
|
||||
instr.src %= 4;
|
||||
asmCode << "\tdivpd " << regE[instr.dst] << ", " << regA[instr.src] << std::endl;
|
||||
asmCode << "\tmaxpd " << regE[instr.dst] << ", " << dblMin << std::endl;
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_ROL_64(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
genbiashift(instr, "rol");
|
||||
gencr(instr);
|
||||
//6 uOPs
|
||||
void AssemblyGeneratorX86::h_FPDIV_M(Instruction& instr, int i) {
|
||||
instr.dst %= 4;
|
||||
genAddressReg(instr);
|
||||
asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
|
||||
asmCode << "\tdivpd " << regE[instr.dst] << ", xmm12" << std::endl;
|
||||
asmCode << "\tmaxpd " << regE[instr.dst] << ", " << dblMin << std::endl;
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_ROR_64(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
genbiashift(instr, "ror");
|
||||
gencr(instr);
|
||||
}
|
||||
//1 uOP
|
||||
void AssemblyGeneratorX86::h_FPSQRT_R(Instruction& instr, int i) {
|
||||
instr.dst %= 4;
|
||||
asmCode << "\tsqrtpd " << regE[instr.dst] << ", " << regE[instr.dst] << std::endl;
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_FPADD(Instruction& instr, int i) {
|
||||
genaf(instr, i);
|
||||
genbf(instr, "addpd");
|
||||
gencf(instr);
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_FPSUB(Instruction& instr, int i) {
|
||||
genaf(instr, i);
|
||||
genbf(instr, "subpd");
|
||||
gencf(instr);
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_FPMUL(Instruction& instr, int i) {
|
||||
genaf(instr, i);
|
||||
genbf(instr, "mulpd");
|
||||
asmCode << "\tmovaps xmm1, xmm0" << std::endl;
|
||||
asmCode << "\tcmpeqpd xmm1, xmm1" << std::endl;
|
||||
asmCode << "\tandps xmm0, xmm1" << std::endl;
|
||||
gencf(instr);
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_FPDIV(Instruction& instr, int i) {
|
||||
genaf(instr, i);
|
||||
genbf(instr, "divpd");
|
||||
asmCode << "\tmovaps xmm1, xmm0" << std::endl;
|
||||
asmCode << "\tcmpeqpd xmm1, xmm1" << std::endl;
|
||||
asmCode << "\tandps xmm0, xmm1" << std::endl;
|
||||
gencf(instr);
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_FPSQRT(Instruction& instr, int i) {
|
||||
genaf(instr, i);
|
||||
asmCode << "\tandps xmm0, xmm10" << std::endl;
|
||||
asmCode << "\tsqrtpd " << regF[instr.regc % RegistersCount] << ", xmm0" << std::endl;
|
||||
gencf(instr, false);
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_FPROUND(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
asmCode << "\tmov rcx, rax" << std::endl;
|
||||
int rotate = (13 - (instr.imm8 & 63)) & 63;
|
||||
//6 uOPs
|
||||
void AssemblyGeneratorX86::h_CFROUND(Instruction& instr, int i) {
|
||||
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
|
||||
int rotate = (13 - (instr.alt & 63)) & 63;
|
||||
if (rotate != 0)
|
||||
asmCode << "\trol rax, " << rotate << std::endl;
|
||||
asmCode << "\tand eax, 24576" << std::endl;
|
||||
asmCode << "\tor eax, 40896" << std::endl;
|
||||
asmCode << "\tmov dword ptr [rsp - 8], eax" << std::endl;
|
||||
asmCode << "\tldmxcsr dword ptr [rsp - 8]" << std::endl;
|
||||
gencr(instr, false);
|
||||
asmCode << "\tmov dword ptr [rsp-8], eax" << std::endl;
|
||||
asmCode << "\tldmxcsr dword ptr [rsp-8]" << std::endl;
|
||||
}
|
||||
|
||||
static inline const char* jumpCondition(Instruction& instr, bool invert = false) {
|
||||
switch ((instr.locb & 7) ^ invert)
|
||||
static inline const char* condition(Instruction& instr, bool invert = false) {
|
||||
switch (((instr.alt >> 2) & 7) ^ invert)
|
||||
{
|
||||
case 0:
|
||||
return "jbe";
|
||||
return "be";
|
||||
case 1:
|
||||
return "ja";
|
||||
return "a";
|
||||
case 2:
|
||||
return "js";
|
||||
return "s";
|
||||
case 3:
|
||||
return "jns";
|
||||
return "ns";
|
||||
case 4:
|
||||
return "jo";
|
||||
return "o";
|
||||
case 5:
|
||||
return "jno";
|
||||
return "no";
|
||||
case 6:
|
||||
return "jl";
|
||||
return "l";
|
||||
case 7:
|
||||
return "jge";
|
||||
return "ge";
|
||||
}
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_JUMP(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
gencr(instr);
|
||||
asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm32 << std::endl;
|
||||
asmCode << "\t" << jumpCondition(instr);
|
||||
asmCode << " rx_i_" << wrapInstr(i + (instr.imm8 & 127) + 2) << std::endl;
|
||||
//4 uOPs
|
||||
void AssemblyGeneratorX86::h_COND_R(Instruction& instr, int i) {
|
||||
asmCode << "\txor ecx, ecx" << std::endl;
|
||||
asmCode << "\tcmp " << regR32[instr.src] << ", " << instr.imm32 << std::endl;
|
||||
asmCode << "\tset" << condition(instr) << " cl" << std::endl;
|
||||
asmCode << "\tadd " << regR[instr.dst] << ", rcx" << std::endl;
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_CALL(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
gencr(instr);
|
||||
asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm32 << std::endl;
|
||||
asmCode << "\t" << jumpCondition(instr, true);
|
||||
asmCode << " short rx_i_" << wrapInstr(i + 1) << std::endl;
|
||||
asmCode << "\tcall rx_i_" << wrapInstr(i + (instr.imm8 & 127) + 2) << std::endl;
|
||||
}
|
||||
|
||||
void AssemblyGeneratorX86::h_RET(Instruction& instr, int i) {
|
||||
genar(instr, i);
|
||||
gencr(instr);
|
||||
asmCode << "\tcmp rsp, " << regStackBeginAddr << std::endl;
|
||||
asmCode << "\tje short rx_i_" << wrapInstr(i + 1) << std::endl;
|
||||
asmCode << "\tret" << std::endl;
|
||||
//6 uOPs
|
||||
void AssemblyGeneratorX86::h_COND_M(Instruction& instr, int i) {
|
||||
asmCode << "\txor ecx, ecx" << std::endl;
|
||||
genAddressReg(instr);
|
||||
asmCode << "\tcmp dword ptr [rsi+rax], " << instr.imm32 << std::endl;
|
||||
asmCode << "\tset" << condition(instr) << " cl" << std::endl;
|
||||
asmCode << "\tadd " << regR[instr.dst] << ", rcx" << std::endl;
|
||||
}
|
||||
|
||||
#include "instructionWeights.hpp"
|
||||
#define INST_HANDLE(x) REPN(&AssemblyGeneratorX86::h_##x, WT(x))
|
||||
|
||||
InstructionGenerator AssemblyGeneratorX86::engine[256] = {
|
||||
INST_HANDLE(ADD_64)
|
||||
INST_HANDLE(ADD_32)
|
||||
INST_HANDLE(SUB_64)
|
||||
INST_HANDLE(SUB_32)
|
||||
INST_HANDLE(MUL_64)
|
||||
INST_HANDLE(MULH_64)
|
||||
INST_HANDLE(MUL_32)
|
||||
INST_HANDLE(IMUL_32)
|
||||
INST_HANDLE(IMULH_64)
|
||||
INST_HANDLE(DIV_64)
|
||||
INST_HANDLE(IDIV_64)
|
||||
INST_HANDLE(AND_64)
|
||||
INST_HANDLE(AND_32)
|
||||
INST_HANDLE(OR_64)
|
||||
INST_HANDLE(OR_32)
|
||||
INST_HANDLE(XOR_64)
|
||||
INST_HANDLE(XOR_32)
|
||||
INST_HANDLE(SHL_64)
|
||||
INST_HANDLE(SHR_64)
|
||||
INST_HANDLE(SAR_64)
|
||||
INST_HANDLE(ROL_64)
|
||||
INST_HANDLE(ROR_64)
|
||||
INST_HANDLE(FPADD)
|
||||
INST_HANDLE(FPSUB)
|
||||
INST_HANDLE(FPMUL)
|
||||
INST_HANDLE(FPDIV)
|
||||
INST_HANDLE(FPSQRT)
|
||||
INST_HANDLE(FPROUND)
|
||||
INST_HANDLE(JUMP)
|
||||
INST_HANDLE(CALL)
|
||||
INST_HANDLE(RET)
|
||||
//Integer
|
||||
INST_HANDLE(IADD_R)
|
||||
INST_HANDLE(IADD_M)
|
||||
INST_HANDLE(IADD_RC)
|
||||
INST_HANDLE(ISUB_R)
|
||||
INST_HANDLE(ISUB_M)
|
||||
INST_HANDLE(IMUL_9C)
|
||||
INST_HANDLE(IMUL_R)
|
||||
INST_HANDLE(IMUL_M)
|
||||
INST_HANDLE(IMULH_R)
|
||||
INST_HANDLE(IMULH_M)
|
||||
INST_HANDLE(ISMULH_R)
|
||||
INST_HANDLE(ISMULH_M)
|
||||
INST_HANDLE(IDIV_C)
|
||||
INST_HANDLE(ISDIV_C)
|
||||
INST_HANDLE(INEG_R)
|
||||
INST_HANDLE(IXOR_R)
|
||||
INST_HANDLE(IXOR_M)
|
||||
INST_HANDLE(IROR_R)
|
||||
INST_HANDLE(IROL_R)
|
||||
|
||||
//Common floating point
|
||||
INST_HANDLE(FPSWAP_R)
|
||||
|
||||
//Floating point group F
|
||||
INST_HANDLE(FPADD_R)
|
||||
INST_HANDLE(FPADD_M)
|
||||
INST_HANDLE(FPSUB_R)
|
||||
INST_HANDLE(FPSUB_M)
|
||||
INST_HANDLE(FPNEG_R)
|
||||
|
||||
//Floating point group E
|
||||
INST_HANDLE(FPMUL_R)
|
||||
INST_HANDLE(FPMUL_M)
|
||||
INST_HANDLE(FPDIV_R)
|
||||
INST_HANDLE(FPDIV_M)
|
||||
INST_HANDLE(FPSQRT_R)
|
||||
|
||||
//Control
|
||||
INST_HANDLE(COND_R)
|
||||
INST_HANDLE(COND_M)
|
||||
INST_HANDLE(CFROUND)
|
||||
};
|
||||
}
|
||||
Reference in New Issue
Block a user