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RandomX portable interpreter
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tevador
336
src/InterpretedVirtualMachine.cpp
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336
src/InterpretedVirtualMachine.cpp
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/*
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Copyright (c) 2018 tevador
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This file is part of RandomX.
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RandomX is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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RandomX is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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*/
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//#define TRACE
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//#define FPUCHECK
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#include "InterpretedVirtualMachine.hpp"
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#include "Pcg32.hpp"
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#include "instructions.hpp"
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#include <iostream>
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#include <iomanip>
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#include <stdexcept>
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#include <sstream>
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#include <cmath>
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#ifdef FPUCHECK
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constexpr bool fpuCheck = true;
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#else
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constexpr bool fpuCheck = false;
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#endif
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namespace RandomX {
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void InterpretedVirtualMachine::initializeProgram(const void* seed) {
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Pcg32 gen(seed);
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for (unsigned i = 0; i < sizeof(reg) / sizeof(Pcg32::result_type); ++i) {
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*(((uint32_t*)®) + i) = gen();
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}
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FPINIT();
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for (int i = 0; i < 8; ++i) {
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reg.f[i].f64 = (double)reg.f[i].i64;
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}
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p.initialize(gen);
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mem.ma = (gen() ^ *(((uint32_t*)seed) + 4)) & ~7;
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mem.mx = *(((uint32_t*)seed) + 5);
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pc = 0;
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ic = InstructionCount;
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stack.clear();
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}
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void InterpretedVirtualMachine::execute() {
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while (ic > 0) {
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auto& inst = p(pc);
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if(trace) std::cout << p.getName(inst) << " (" << std::dec << pc << ")" << std::endl;
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pc = (pc + 1) % ProgramLength;
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auto handler = engine[inst.opcode];
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(this->*handler)(inst);
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ic--;
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}
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}
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convertible_t InterpretedVirtualMachine::loada(Instruction& inst) {
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convertible_t& rega = reg.r[inst.rega % RegistersCount];
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rega.u64 ^= inst.addr0;
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addr_t addr = rega.u32;
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switch (inst.loca & 7)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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return readDataset(addr, mem);
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case 4:
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return scratchpad[addr % ScratchpadL2];
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case 5:
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case 6:
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case 7:
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return scratchpad[addr % ScratchpadL1];
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}
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}
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convertible_t InterpretedVirtualMachine::loadbr1(Instruction& inst) {
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switch (inst.loca & 7)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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return reg.r[inst.regb % RegistersCount];
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case 6:
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case 7:
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convertible_t temp;
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temp.i64 = inst.imm1;
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return temp;
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}
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}
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convertible_t InterpretedVirtualMachine::loadbr0(Instruction& inst) {
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switch (inst.locb & 7)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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return reg.r[inst.regb % RegistersCount];
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case 6:
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case 7:
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convertible_t temp;
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temp.u64 = inst.imm0;
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return temp;
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}
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}
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double InterpretedVirtualMachine::loadbf(Instruction& inst) {
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switch (inst.locb & 7)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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return reg.f[inst.regb % RegistersCount].f64;
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case 6:
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case 7:
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return (double)inst.imm1;
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}
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}
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convertible_t& InterpretedVirtualMachine::getcr(Instruction& inst) {
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addr_t addr;
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switch (inst.locc & 7)
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{
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case 0:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addr1;
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return scratchpad[addr % ScratchpadL2];
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case 1:
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case 2:
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case 3:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addr1;
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return scratchpad[addr % ScratchpadL1];
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case 4:
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case 5:
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case 6:
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case 7:
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return reg.r[inst.regc % RegistersCount];
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}
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}
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convertible_t& InterpretedVirtualMachine::getcf(Instruction& inst) {
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addr_t addr;
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switch (inst.locc & 7)
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{
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case 0:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addr1;
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return scratchpad[addr % ScratchpadL2];
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case 1:
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case 2:
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case 3:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addr1;
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return scratchpad[addr % ScratchpadL1];
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case 4:
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case 5:
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case 6:
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case 7:
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return reg.f[inst.regc % RegistersCount];
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}
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}
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#define ALU_RETIRE(x) x(a, b, c); \
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if(trace) std::cout << std::hex << a.u64 << " " << b.u64 << " " << c.u64 << std::endl;
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#define FPU_RETIRE(x) x(a, b, c); \
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if(trace) { \
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convertible_t bc; \
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bc.f64 = b; \
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std::cout << std::hex << a.u64 << " " << bc.u64 << " " << c.u64 << std::endl; \
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} \
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if(fpuCheck) { \
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convertible_t bc; \
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if(c.f64 != c.f64) { \
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std::stringstream ss; \
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bc.f64 = b; \
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ss << "NaN result of " << #x << "(" << std::hex << a.u64 << ", " << bc.u64 << ") = " << c.u64; \
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throw std::runtime_error(ss.str()); \
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} else if (std::fpclassify(c.f64) == FP_SUBNORMAL) {\
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std::stringstream ss; \
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bc.f64 = b; \
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ss << "Denormal result of " << #x << "(" << std::hex << a.u64 << ", " << bc.u64 << ") = " << c.u64; \
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throw std::runtime_error(ss.str()); \
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} \
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}
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#define FPU_RETIRE_NB(x) x(a, b, c); \
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if(trace) std::cout << std::hex << a.u64 << " " << c.u64 << std::endl;
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#define ALU_INST(x) void InterpretedVirtualMachine::h_##x(Instruction& inst) { \
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convertible_t a = loada(inst); \
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convertible_t b = loadbr1(inst); \
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convertible_t& c = getcr(inst); \
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ALU_RETIRE(x) \
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}
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#define ALU_INST_SR(x) void InterpretedVirtualMachine::h_##x(Instruction& inst) { \
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convertible_t a = loada(inst); \
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convertible_t b = loadbr0(inst); \
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convertible_t& c = getcr(inst); \
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ALU_RETIRE(x) \
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}
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#define FPU_INST(x) void InterpretedVirtualMachine::h_##x(Instruction& inst) { \
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convertible_t a = loada(inst); \
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double b = loadbf(inst); \
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convertible_t& c = getcf(inst); \
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FPU_RETIRE(x) \
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}
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#define FPU_INST_NB(x) void InterpretedVirtualMachine::h_##x(Instruction& inst) { \
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convertible_t a = loada(inst); \
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convertible_t b; \
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convertible_t& c = getcf(inst); \
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FPU_RETIRE_NB(x) \
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}
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ALU_INST(ADD_64)
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ALU_INST(ADD_32)
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ALU_INST(SUB_64)
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ALU_INST(SUB_32)
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ALU_INST(MUL_64)
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ALU_INST(MULH_64)
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ALU_INST(MUL_32)
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ALU_INST(IMUL_32)
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ALU_INST(IMULH_64)
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ALU_INST(DIV_64)
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ALU_INST(IDIV_64)
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ALU_INST(AND_64)
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ALU_INST(AND_32)
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ALU_INST(OR_64)
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ALU_INST(OR_32)
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ALU_INST(XOR_64)
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ALU_INST(XOR_32)
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ALU_INST_SR(SHL_64)
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ALU_INST_SR(SHR_64)
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ALU_INST_SR(SAR_64)
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ALU_INST_SR(ROL_64)
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ALU_INST_SR(ROR_64)
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FPU_INST(FPADD)
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FPU_INST(FPSUB)
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FPU_INST(FPMUL)
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FPU_INST(FPDIV)
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FPU_INST_NB(FPSQRT)
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FPU_INST_NB(FPROUND)
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void InterpretedVirtualMachine::h_CALL(Instruction& inst) {
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convertible_t a = loada(inst);
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convertible_t b = loadbr1(inst);
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convertible_t& c = getcr(inst);
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if (b.u32 <= (uint32_t)inst.imm1) {
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stackPush(a);
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stackPush(pc);
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pc += (inst.imm0 & 127) + 1;
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pc = pc % ProgramLength;
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}
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else {
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c.u64 = a.u64;
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}
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}
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void InterpretedVirtualMachine::h_RET(Instruction& inst) {
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convertible_t a = loada(inst);
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convertible_t b = loadbr1(inst);
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convertible_t& c = getcr(inst);
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if (stack.size() > 0 && b.u32 <= (uint32_t)inst.imm1) {
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auto raddr = stackPopAddress();
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auto retval = stackPopValue();
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c.u64 = a.u64 ^ retval.u64;
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pc = raddr;
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}
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else {
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c.u64 = a.u64;
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}
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}
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#include "instructionWeights.hpp"
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#define INST_HANDLE(x) REPN(&InterpretedVirtualMachine::h_##x, WT(x))
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InstructionHandler InterpretedVirtualMachine::engine[256] = {
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INST_HANDLE(ADD_64)
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INST_HANDLE(ADD_32)
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INST_HANDLE(SUB_64)
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INST_HANDLE(SUB_32)
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INST_HANDLE(MUL_64)
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INST_HANDLE(MULH_64)
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INST_HANDLE(MUL_32)
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INST_HANDLE(IMUL_32)
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INST_HANDLE(IMULH_64)
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INST_HANDLE(DIV_64)
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INST_HANDLE(IDIV_64)
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INST_HANDLE(AND_64)
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INST_HANDLE(AND_32)
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INST_HANDLE(OR_64)
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INST_HANDLE(OR_32)
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INST_HANDLE(XOR_64)
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INST_HANDLE(XOR_32)
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INST_HANDLE(SHL_64)
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INST_HANDLE(SHR_64)
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INST_HANDLE(SAR_64)
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INST_HANDLE(ROL_64)
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INST_HANDLE(ROR_64)
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INST_HANDLE(FPADD)
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INST_HANDLE(FPSUB)
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INST_HANDLE(FPMUL)
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INST_HANDLE(FPDIV)
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INST_HANDLE(FPSQRT)
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INST_HANDLE(FPROUND)
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INST_HANDLE(CALL)
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INST_HANDLE(RET)
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};
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}
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