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https://codeberg.org/wownero/RandomWOW
synced 2026-03-05 14:17:33 -05:00
Interpreter + async mode
This commit is contained in:
tevador
@@ -21,11 +21,15 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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#include "InterpretedVirtualMachine.hpp"
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#include "Pcg32.hpp"
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#include "instructions.hpp"
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#include "dataset.hpp"
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#include "Cache.hpp"
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#include "LightClientAsyncWorker.hpp"
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#include <iostream>
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#include <iomanip>
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#include <stdexcept>
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#include <sstream>
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#include <cmath>
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#include <thread>
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#ifdef STATS
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#include <algorithm>
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#endif
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@@ -38,6 +42,57 @@ constexpr bool fpuCheck = false;
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namespace RandomX {
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InterpretedVirtualMachine::~InterpretedVirtualMachine() {
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if (asyncWorker) {
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delete mem.ds.asyncWorker;
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}
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}
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void InterpretedVirtualMachine::setDataset(dataset_t ds) {
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if (asyncWorker) {
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if (softAes) {
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mem.ds.asyncWorker = new LightClientAsyncWorker<true>(ds.cache);
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}
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else {
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mem.ds.asyncWorker = new LightClientAsyncWorker<false>(ds.cache);
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}
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readDataset = &datasetReadLightAsync;
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}
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else {
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mem.ds = ds;
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if (softAes) {
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readDataset = &datasetReadLight<true>;
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}
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else {
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readDataset = &datasetReadLight<false>;
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}
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}
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}
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void InterpretedVirtualMachine::initializeScratchpad(uint32_t index) {
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uint32_t startingBlock = (ScratchpadSize / CacheLineSize) * index;
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if (asyncWorker) {
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ILightClientAsyncWorker* worker = mem.ds.asyncWorker;
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const uint32_t blocksPerThread = (ScratchpadSize / CacheLineSize) / 2;
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worker->prepareBlocks(scratchpad, startingBlock, blocksPerThread); //async first half
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worker->getBlocks(scratchpad + ScratchpadLength / 2, startingBlock + blocksPerThread, blocksPerThread); //sync second half
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worker->sync();
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}
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else {
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auto cache = mem.ds.cache;
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if (softAes) {
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for (int i = 0; i < ScratchpadSize / CacheLineSize; ++i) {
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initBlock<true>(cache->getCache(), ((uint8_t*)scratchpad) + CacheLineSize * i, (ScratchpadSize / CacheLineSize) * index + i, cache->getKeys());
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}
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}
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else {
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for (int i = 0; i < ScratchpadSize / CacheLineSize; ++i) {
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initBlock<false>(cache->getCache(), ((uint8_t*)scratchpad) + CacheLineSize * i, (ScratchpadSize / CacheLineSize) * index + i, cache->getKeys());
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}
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}
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}
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}
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void InterpretedVirtualMachine::initializeProgram(const void* seed) {
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Pcg32 gen(seed);
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for (unsigned i = 0; i < sizeof(reg) / sizeof(Pcg32::result_type); ++i) {
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@@ -50,6 +105,7 @@ namespace RandomX {
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}
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//std::cout << reg;
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p.initialize(gen);
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currentTransform = addressTransformations[gen.getUniform(0, TransformationCount - 1)];
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mem.ma = (gen() ^ *(((uint32_t*)seed) + 4)) & ~7;
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mem.mx = *(((uint32_t*)seed) + 5);
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pc = 0;
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@@ -74,61 +130,61 @@ namespace RandomX {
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#endif
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}
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convertible_t InterpretedVirtualMachine::loada(Instruction& inst) {
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convertible_t& rega = reg.r[inst.rega % RegistersCount];
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rega.i64 ^= inst.addra; //sign-extend addra
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convertible_t InterpretedVirtualMachine::loada(Instruction& instr) {
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convertible_t& rega = reg.r[instr.rega % RegistersCount];
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rega.i64 ^= instr.addra; //sign-extend addra
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addr_t addr = rega.u32;
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switch (inst.loca & 7)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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return readDataset(addr, mem);
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case 4:
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return scratchpad[addr % ScratchpadL2];
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if ((ic % 64) == 0) {
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addr = currentTransform->apply(addr);
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#ifdef STATS
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datasetAccess[mem.ma / (DatasetBlockCount / 256) / CacheLineSize]++;
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#endif
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readDataset(addr, mem, reg);
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}
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case 5:
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case 6:
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case 7:
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return scratchpad[addr % ScratchpadL1];
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if ((instr.loca & 192) == 0) {
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mem.mx ^= addr;
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}
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if (instr.loca & 3) {
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return scratchpad[addr % ScratchpadL1];
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}
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else {
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return scratchpad[addr % ScratchpadL2];
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}
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}
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convertible_t InterpretedVirtualMachine::loadbr1(Instruction& inst) {
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switch (inst.locb & 7)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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return reg.r[inst.regb % RegistersCount];
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case 6:
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case 7:
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convertible_t temp;
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temp.i64 = inst.imm32; //sign-extend imm32
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return temp;
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convertible_t InterpretedVirtualMachine::loadbia(Instruction& instr) {
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if (instr.locb & 3) {
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return reg.r[instr.regb % RegistersCount];
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}
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else {
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convertible_t temp;
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temp.i64 = instr.imm32; //sign-extend imm32
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return temp;
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}
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}
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convertible_t InterpretedVirtualMachine::loadbr0(Instruction& inst) {
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switch (inst.locb & 7)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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return reg.r[inst.regb % RegistersCount];
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case 4:
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case 5:
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case 6:
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case 7:
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convertible_t temp;
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temp.u64 = inst.imm8;
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return temp;
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convertible_t InterpretedVirtualMachine::loadbiashift(Instruction& instr) {
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if (instr.locb & 1) {
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return reg.r[instr.regb % RegistersCount];
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}
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else {
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convertible_t temp;
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temp.u64 = instr.imm8;
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return temp;
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}
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}
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convertible_t InterpretedVirtualMachine::loadbiadiv(Instruction& instr) {
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if (instr.locb & 3) {
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convertible_t temp;
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temp.u64 = instr.imm32;
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return temp;
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}
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else {
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return reg.r[instr.regb % RegistersCount];
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}
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}
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@@ -174,26 +230,6 @@ namespace RandomX {
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}
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}
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void InterpretedVirtualMachine::writecflo(Instruction& inst, fpu_reg_t& regc) {
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addr_t addr;
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switch (inst.locc & 7)
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{
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case 4:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addrc;
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scratchpad[addr % ScratchpadL2] = regc.lo;
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break;
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case 5:
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case 6:
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case 7:
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addr = reg.r[inst.regc % RegistersCount].u32 ^ inst.addrc;
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scratchpad[addr % ScratchpadL1] = regc.lo;
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default:
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break;
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}
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}
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#define ALU_RETIRE(x) x(a, b, c); \
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if(trace) std::cout << std::hex << /*a.u64 << " " << b.u64 << " " <<*/ c.u64 << std::endl;
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@@ -242,7 +278,7 @@ namespace RandomX {
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#define ALU_INST(x) void InterpretedVirtualMachine::h_##x(Instruction& inst) { \
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INC_COUNT(x) \
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convertible_t a = loada(inst); \
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convertible_t b = loadbr1(inst); \
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convertible_t b = loadbia(inst); \
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convertible_t& c = getcr(inst); \
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ALU_RETIRE(x) \
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}
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@@ -250,7 +286,15 @@ namespace RandomX {
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#define ALU_INST_SR(x) void InterpretedVirtualMachine::h_##x(Instruction& inst) { \
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INC_COUNT(x) \
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convertible_t a = loada(inst); \
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convertible_t b = loadbr0(inst); \
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convertible_t b = loadbiashift(inst); \
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convertible_t& c = getcr(inst); \
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ALU_RETIRE(x) \
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}
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#define ALU_INST_DIV(x) void InterpretedVirtualMachine::h_##x(Instruction& inst) { \
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INC_COUNT(x) \
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convertible_t a = loada(inst); \
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convertible_t b = loadbiadiv(inst); \
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convertible_t& c = getcr(inst); \
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ALU_RETIRE(x) \
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}
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@@ -282,8 +326,8 @@ namespace RandomX {
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ALU_INST(MUL_32)
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ALU_INST(IMUL_32)
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ALU_INST(IMULH_64)
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ALU_INST(DIV_64)
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ALU_INST(IDIV_64)
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ALU_INST_DIV(DIV_64)
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ALU_INST_DIV(IDIV_64)
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ALU_INST(AND_64)
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ALU_INST(AND_32)
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ALU_INST(OR_64)
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@@ -301,42 +345,68 @@ namespace RandomX {
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FPU_INST(FPSUB)
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FPU_INST(FPMUL)
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FPU_INST(FPDIV)
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FPU_INST_NB(FPSQRT)
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FPU_INST_NB(FPROUND)
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void InterpretedVirtualMachine::h_FPROUND(Instruction& inst) {
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convertible_t a = loada(inst);
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convertible_t& c = getcr(inst);
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c.u64 = a.u64;
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if (trace) std::cout << std::hex << a.u64 << std::endl;
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FPROUND(a, inst.imm8);
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}
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void InterpretedVirtualMachine::h_JUMP(Instruction& inst) {
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convertible_t a = loada(inst);
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convertible_t& c = getcr(inst);
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c.u64 = a.u64;
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if (trace) std::cout << std::hex << a.u64 << std::endl;
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if (JMP_COND(inst.locb, reg.r[inst.regb % RegistersCount], inst.imm32)) {
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#ifdef STATS
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count_JUMP_taken++;
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count_jump_taken[inst.locb & 7]++;
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#endif
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pc += (inst.imm8 & 127) + 1;
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pc = pc % ProgramLength;
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}
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#ifdef STATS
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else {
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count_JUMP_not_taken++;
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count_jump_not_taken[inst.locb & 7]++;
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}
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#endif
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}
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void InterpretedVirtualMachine::h_CALL(Instruction& inst) {
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convertible_t a = loada(inst);
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convertible_t& c = getcr(inst);
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c.u64 = a.u64;
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if (trace) std::cout << std::hex << a.u64 << std::endl;
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if (JMP_COND(inst.locb, reg.r[inst.regb % RegistersCount], inst.imm32)) {
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#ifdef STATS
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count_CALL_taken++;
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count_jump_taken[inst.locb & 7]++;
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count_retdepth = std::max(0, count_retdepth - 1);
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#endif
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stackPush(a);
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stackPush(pc);
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#ifdef STATS
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count_max_stack = std::max(count_max_stack, (int)stack.size());
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#endif
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pc += (inst.imm8 & 127) + 1;
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pc = pc % ProgramLength;
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if (trace) std::cout << std::hex << a.u64 << std::endl;
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}
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else {
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convertible_t& c = getcr(inst);
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#ifdef STATS
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else {
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count_CALL_not_taken++;
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count_jump_not_taken[inst.locb & 7]++;
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#endif
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c.u64 = a.u64;
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if (trace) std::cout << std::hex << /*a.u64 << " " <<*/ c.u64 << std::endl;
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}
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#endif
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}
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void InterpretedVirtualMachine::h_RET(Instruction& inst) {
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convertible_t a = loada(inst);
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convertible_t b = loadbr1(inst);
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convertible_t& c = getcr(inst);
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c.u64 = a.u64;
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if (trace) std::cout << std::hex << a.u64 << std::endl;
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if (stack.size() > 0) {
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#ifdef STATS
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count_RET_taken++;
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@@ -344,22 +414,13 @@ namespace RandomX {
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count_retdepth_max = std::max(count_retdepth_max, count_retdepth);
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#endif
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auto raddr = stackPopAddress();
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auto retval = stackPopValue();
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c.u64 = a.u64 ^ retval.u64;
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pc = raddr;
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}
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else {
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#ifdef STATS
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if (stack.size() == 0)
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count_RET_stack_empty++;
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else {
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count_RET_not_taken++;
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count_jump_not_taken[inst.locb & 7]++;
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}
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#endif
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c.u64 = a.u64;
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else {
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count_RET_stack_empty++;
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}
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if (trace) std::cout << std::hex << /*a.u64 << " " <<*/ c.u64 << std::endl;
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#endif
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}
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#include "instructionWeights.hpp"
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@@ -394,6 +455,7 @@ namespace RandomX {
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INST_HANDLE(FPDIV)
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INST_HANDLE(FPSQRT)
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INST_HANDLE(FPROUND)
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INST_HANDLE(JUMP)
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INST_HANDLE(CALL)
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INST_HANDLE(RET)
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};
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