mirror of
https://codeberg.org/wownero/RandomWOW
synced 2026-03-05 14:17:33 -05:00
Interpreter with bytecode
Fixed some undefined behavior with signed types Fixed different results on big endian systems Removed unused code files Restored FNEG_R instructions Updated documentation
This commit is contained in:
tevador
@@ -19,7 +19,6 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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//#define TRACE
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//#define FPUCHECK
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#include "InterpretedVirtualMachine.hpp"
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#include "Pcg32.hpp"
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#include "instructions.hpp"
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#include "dataset.hpp"
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#include "Cache.hpp"
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@@ -34,6 +33,7 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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#ifdef STATS
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#include <algorithm>
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#endif
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#include "divideByConstantCodegen.h"
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#ifdef FPUCHECK
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constexpr bool fpuCheck = true;
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@@ -61,88 +61,683 @@ namespace RandomX {
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}
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else {
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mem.ds = ds;
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if (softAes) {
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readDataset = &datasetReadLight<true>;
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}
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else {
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readDataset = &datasetReadLight<false>;
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}
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readDataset = &datasetReadLight;
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}
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}
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void InterpretedVirtualMachine::initializeScratchpad(uint8_t* scratchpad, int32_t index) {
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uint32_t startingBlock = (ScratchpadSize / CacheLineSize) * index;
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if (asyncWorker) {
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ILightClientAsyncWorker* worker = mem.ds.asyncWorker;
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const uint32_t blocksPerThread = (ScratchpadSize / CacheLineSize) / 2;
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worker->prepareBlocks(scratchpad, startingBlock, blocksPerThread); //async first half
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worker->getBlocks(scratchpad + ScratchpadLength / 2, startingBlock + blocksPerThread, blocksPerThread); //sync second half
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worker->sync();
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}
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else {
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auto cache = mem.ds.cache;
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if (softAes) {
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for (int i = 0; i < ScratchpadSize / CacheLineSize; ++i) {
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initBlock<true>(cache->getCache(), ((uint8_t*)scratchpad) + CacheLineSize * i, (ScratchpadSize / CacheLineSize) * index + i, cache->getKeys());
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}
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}
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else {
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for (int i = 0; i < ScratchpadSize / CacheLineSize; ++i) {
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initBlock<false>(cache->getCache(), ((uint8_t*)scratchpad) + CacheLineSize * i, (ScratchpadSize / CacheLineSize) * index + i, cache->getKeys());
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}
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}
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void InterpretedVirtualMachine::initialize() {
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VirtualMachine::initialize();
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for (unsigned i = 0; i < ProgramLength; ++i) {
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program(i).src %= RegistersCount;
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program(i).dst %= RegistersCount;
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}
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}
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void InterpretedVirtualMachine::initializeProgram(const void* seed) {
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Pcg32 gen(seed);
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for (unsigned i = 0; i < sizeof(reg) / sizeof(Pcg32::result_type); ++i) {
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*(((uint32_t*)®) + i) = gen();
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template<int N>
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void InterpretedVirtualMachine::executeBytecode(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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executeBytecode(N, r, f, e, a);
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executeBytecode<N + 1>(r, f, e, a);
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}
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template<>
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void InterpretedVirtualMachine::executeBytecode<ProgramLength>(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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}
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FORCE_INLINE void InterpretedVirtualMachine::executeBytecode(int i, int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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auto& ibc = byteCode[i];
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switch (ibc.type)
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{
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case InstructionType::IADD_R: {
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*ibc.idst += *ibc.isrc;
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} break;
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case InstructionType::IADD_M: {
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*ibc.idst += load64(scratchpad + (*ibc.isrc & ibc.memMask));
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} break;
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case InstructionType::IADD_RC: {
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*ibc.idst += *ibc.isrc + ibc.imm;
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} break;
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case InstructionType::ISUB_R: {
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*ibc.idst -= *ibc.isrc;
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} break;
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case InstructionType::ISUB_M: {
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*ibc.idst -= load64(scratchpad + (*ibc.isrc & ibc.memMask));
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} break;
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case InstructionType::IMUL_9C: {
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*ibc.idst += 9 * *ibc.idst + ibc.imm;
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} break;
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case InstructionType::IMUL_R: {
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*ibc.idst *= *ibc.isrc;
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} break;
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case InstructionType::IMUL_M: {
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*ibc.idst *= load64(scratchpad + (*ibc.isrc & ibc.memMask));
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} break;
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case InstructionType::IMULH_R: {
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*ibc.idst = mulh(*ibc.idst, *ibc.isrc);
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} break;
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case InstructionType::IMULH_M: {
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*ibc.idst = mulh(*ibc.idst, load64(scratchpad + (*ibc.isrc & ibc.memMask)));
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} break;
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case InstructionType::ISMULH_R: {
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*ibc.idst = smulh(unsigned64ToSigned2sCompl(*ibc.idst), unsigned64ToSigned2sCompl(*ibc.isrc));
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} break;
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case InstructionType::ISMULH_M: {
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*ibc.idst = smulh(unsigned64ToSigned2sCompl(*ibc.idst), unsigned64ToSigned2sCompl(load64(scratchpad + (*ibc.isrc & ibc.memMask))));
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} break;
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case InstructionType::IDIV_C: {
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if (ibc.signedMultiplier != 0) {
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int_reg_t dividend = *ibc.idst;
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int_reg_t quotient = dividend >> ibc.preShift;
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if (ibc.increment) {
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quotient = quotient == UINT64_MAX ? UINT64_MAX : quotient + 1;
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}
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quotient = mulh(quotient, ibc.signedMultiplier);
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quotient >>= ibc.postShift;
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*ibc.idst += quotient;
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}
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else {
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*ibc.idst += *ibc.idst >> ibc.shift;
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}
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} break;
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case InstructionType::ISDIV_C: {
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} break;
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case InstructionType::INEG_R: {
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*ibc.idst = ~(*ibc.idst) + 1; //two's complement negative
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} break;
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case InstructionType::IXOR_R: {
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*ibc.idst ^= *ibc.isrc;
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} break;
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case InstructionType::IXOR_M: {
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*ibc.idst ^= load64(scratchpad + (*ibc.isrc & ibc.memMask));
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} break;
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case InstructionType::IROR_R: {
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*ibc.idst = rotr(*ibc.idst, *ibc.isrc & 63);
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} break;
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case InstructionType::IROL_R: {
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*ibc.idst = rotl(*ibc.idst, *ibc.isrc & 63);
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} break;
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case InstructionType::ISWAP_R: {
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int_reg_t temp = *ibc.isrc;
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*ibc.isrc = *ibc.idst;
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*ibc.idst = temp;
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} break;
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case InstructionType::FSWAP_R: {
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*ibc.fdst = _mm_shuffle_pd(*ibc.fdst, *ibc.fdst, 1);
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} break;
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case InstructionType::FADD_R: {
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*ibc.fdst = _mm_add_pd(*ibc.fdst, *ibc.fsrc);
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} break;
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case InstructionType::FADD_M: {
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__m128d fsrc = load_cvt_i32x2(scratchpad + (*ibc.isrc & ibc.memMask));
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*ibc.fdst = _mm_add_pd(*ibc.fdst, fsrc);
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} break;
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case InstructionType::FSUB_R: {
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*ibc.fdst = _mm_sub_pd(*ibc.fdst, *ibc.fsrc);
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} break;
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case InstructionType::FSUB_M: {
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__m128d fsrc = load_cvt_i32x2(scratchpad + (*ibc.isrc & ibc.memMask));
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*ibc.fdst = _mm_sub_pd(*ibc.fdst, fsrc);
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} break;
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case InstructionType::FNEG_R: {
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const __m128d signMask = _mm_castsi128_pd(_mm_set1_epi64x(1ULL << 63));
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*ibc.fdst = _mm_xor_pd(*ibc.fdst, signMask);
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} break;
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case InstructionType::FMUL_R: {
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*ibc.fdst = _mm_mul_pd(*ibc.fdst, *ibc.fsrc);
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} break;
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case InstructionType::FDIV_M: {
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__m128d fsrc = load_cvt_i32x2(scratchpad + (*ibc.isrc & ibc.memMask));
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__m128d fdst = _mm_div_pd(*ibc.fdst, fsrc);
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*ibc.fdst = _mm_max_pd(fdst, _mm_set_pd(DBL_MIN, DBL_MIN));
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} break;
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case InstructionType::FSQRT_R: {
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*ibc.fdst = _mm_sqrt_pd(*ibc.fdst);
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} break;
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case InstructionType::COND_R: {
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*ibc.idst += condition(*ibc.isrc, ibc.imm, ibc.condition) ? 1 : 0;
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} break;
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case InstructionType::COND_M: {
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*ibc.idst += condition(load64(scratchpad + (*ibc.isrc & ibc.memMask)), ibc.imm, ibc.condition) ? 1 : 0;
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} break;
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case InstructionType::CFROUND: {
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setRoundMode(rotr(*ibc.isrc, ibc.imm) % 4);
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} break;
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case InstructionType::ISTORE: {
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store64(scratchpad + (*ibc.idst & ibc.memMask), *ibc.isrc);
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} break;
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case InstructionType::NOP: {
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//nothing
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} break;
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default:
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UNREACHABLE;
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}
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initFpu();
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for (int i = 0; i < RegistersCount; ++i) {
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reg.f[i].lo.f64 = (double)reg.f[i].lo.i64;
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reg.f[i].hi.f64 = (double)reg.f[i].hi.i64;
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}
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//std::cout << reg;
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p.initialize(gen);
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currentTransform = addressTransformations[gen.getUniform(0, TransformationCount - 1)];
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mem.ma = (gen() ^ *(((uint32_t*)seed) + 4)) & ~7;
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mem.mx = *(((uint32_t*)seed) + 5);
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pc = 0;
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ic = InstructionCount;
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stack.clear();
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}
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void InterpretedVirtualMachine::execute() {
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for(int i = 0; i < InstructionCount; ++i) {
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for (int j = 0; j < ProgramLength; ++j) {
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auto& ibc = byteCode[j];
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switch (ibc.type)
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{
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case InstructionType::CFROUND: {
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uint64_t rcFlag = rotr(ibc.isrc->u64, ibc.imm.i32);
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setRoundMode(rcFlag);
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}
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break;
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}
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int_reg_t r[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
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__m128d f[4];
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__m128d e[4];
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__m128d a[4];
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a[0] = _mm_load_pd(®.a[0].lo);
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a[1] = _mm_load_pd(®.a[1].lo);
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a[2] = _mm_load_pd(®.a[2].lo);
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a[3] = _mm_load_pd(®.a[3].lo);
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precompileProgram(r, f, e, a);
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uint32_t spAddr0 = mem.mx;
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uint32_t spAddr1 = mem.ma;
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for(int iter = 0; iter < InstructionCount; ++iter) {
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//std::cout << "Iteration " << iter << std::endl;
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spAddr0 ^= r[readReg0];
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spAddr0 &= ScratchpadL3Mask64;
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r[0] ^= load64(scratchpad + spAddr0 + 0);
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r[1] ^= load64(scratchpad + spAddr0 + 8);
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r[2] ^= load64(scratchpad + spAddr0 + 16);
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r[3] ^= load64(scratchpad + spAddr0 + 24);
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r[4] ^= load64(scratchpad + spAddr0 + 32);
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r[5] ^= load64(scratchpad + spAddr0 + 40);
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r[6] ^= load64(scratchpad + spAddr0 + 48);
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r[7] ^= load64(scratchpad + spAddr0 + 56);
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spAddr1 ^= r[readReg1];
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spAddr1 &= ScratchpadL3Mask64;
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f[0] = load_cvt_i32x2(scratchpad + spAddr1 + 0);
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f[1] = load_cvt_i32x2(scratchpad + spAddr1 + 8);
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f[2] = load_cvt_i32x2(scratchpad + spAddr1 + 16);
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f[3] = load_cvt_i32x2(scratchpad + spAddr1 + 24);
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e[0] = _mm_abs(load_cvt_i32x2(scratchpad + spAddr1 + 32));
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e[1] = _mm_abs(load_cvt_i32x2(scratchpad + spAddr1 + 40));
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e[2] = _mm_abs(load_cvt_i32x2(scratchpad + spAddr1 + 48));
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e[3] = _mm_abs(load_cvt_i32x2(scratchpad + spAddr1 + 56));
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executeBytecode<0>(r, f, e, a);
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if (asyncWorker) {
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ILightClientAsyncWorker* aw = mem.ds.asyncWorker;
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const uint64_t* datasetLine = aw->getBlock(mem.ma);
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for (int i = 0; i < RegistersCount; ++i)
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r[i] ^= datasetLine[i];
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mem.mx ^= r[readReg2] ^ r[readReg3];
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mem.mx &= CacheLineAlignMask; //align to cache line
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std::swap(mem.mx, mem.ma);
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aw->prepareBlock(mem.ma);
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}
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else {
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mem.mx ^= r[readReg2] ^ r[readReg3];
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mem.mx &= CacheLineAlignMask;
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Cache* cache = mem.ds.cache;
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uint64_t datasetLine[CacheLineSize / sizeof(uint64_t)];
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initBlock(cache->getCache(), (uint8_t*)datasetLine, mem.ma / CacheLineSize, cache->getKeys());
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for (int i = 0; i < RegistersCount; ++i)
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r[i] ^= datasetLine[i];
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std::swap(mem.mx, mem.ma);
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}
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store64(scratchpad + spAddr1 + 0, r[0]);
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store64(scratchpad + spAddr1 + 8, r[1]);
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store64(scratchpad + spAddr1 + 16, r[2]);
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store64(scratchpad + spAddr1 + 24, r[3]);
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store64(scratchpad + spAddr1 + 32, r[4]);
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store64(scratchpad + spAddr1 + 40, r[5]);
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store64(scratchpad + spAddr1 + 48, r[6]);
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store64(scratchpad + spAddr1 + 56, r[7]);
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_mm_store_pd((double*)(scratchpad + spAddr0 + 0), _mm_mul_pd(f[0], e[0]));
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_mm_store_pd((double*)(scratchpad + spAddr0 + 16), _mm_mul_pd(f[1], e[1]));
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_mm_store_pd((double*)(scratchpad + spAddr0 + 32), _mm_mul_pd(f[2], e[2]));
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_mm_store_pd((double*)(scratchpad + spAddr0 + 48), _mm_mul_pd(f[3], e[3]));
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spAddr0 = 0;
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spAddr1 = 0;
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}
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store64(®.r[0], r[0]);
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store64(®.r[1], r[1]);
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store64(®.r[2], r[2]);
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store64(®.r[3], r[3]);
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store64(®.r[4], r[4]);
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store64(®.r[5], r[5]);
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store64(®.r[6], r[6]);
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store64(®.r[7], r[7]);
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_mm_store_pd(®.f[0].lo, f[0]);
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_mm_store_pd(®.f[1].lo, f[1]);
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_mm_store_pd(®.f[2].lo, f[2]);
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_mm_store_pd(®.f[3].lo, f[3]);
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_mm_store_pd(®.e[0].lo, e[0]);
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_mm_store_pd(®.e[1].lo, e[1]);
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_mm_store_pd(®.e[2].lo, e[2]);
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_mm_store_pd(®.e[3].lo, e[3]);
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}
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#include "instructionWeights.hpp"
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void InterpretedVirtualMachine::executeInstruction(Instruction& instr) {
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switch (instr.opcode)
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{
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CASE_REP(IADD_R)
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void InterpretedVirtualMachine::precompileProgram(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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for (unsigned i = 0; i < ProgramLength; ++i) {
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auto& instr = program(i);
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auto& ibc = byteCode[i];
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switch (instr.opcode) {
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CASE_REP(IADD_R) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IADD_R;
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ibc.idst = &r[dst];
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if (src != dst) {
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ibc.isrc = &r[src];
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}
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else {
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ibc.imm = signExtend2sCompl(instr.imm32);
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ibc.isrc = &ibc.imm;
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}
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} break;
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break;
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CASE_REP(IADD_M) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IADD_M;
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ibc.idst = &r[dst];
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if (instr.src != instr.dst) {
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ibc.isrc = &r[src];
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ibc.memMask = ((instr.mod % 4) ? ScratchpadL1Mask : ScratchpadL2Mask);
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}
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else {
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ibc.imm = instr.imm32;
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ibc.isrc = &ibc.imm;
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ibc.memMask = ScratchpadL3Mask;
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}
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} break;
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CASE_REP(IADD_RC) {
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auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::IADD_RC;
|
||||
ibc.idst = &r[dst];
|
||||
ibc.isrc = &r[src];
|
||||
ibc.imm = signExtend2sCompl(instr.imm32);
|
||||
} break;
|
||||
|
||||
CASE_REP(ISUB_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::ISUB_R;
|
||||
ibc.idst = &r[dst];
|
||||
if (src != dst) {
|
||||
ibc.isrc = &r[src];
|
||||
}
|
||||
else {
|
||||
ibc.imm = signExtend2sCompl(instr.imm32);
|
||||
ibc.isrc = &ibc.imm;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(ISUB_M) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::ISUB_M;
|
||||
ibc.idst = &r[dst];
|
||||
if (instr.src != instr.dst) {
|
||||
ibc.isrc = &r[src];
|
||||
ibc.memMask = ((instr.mod % 4) ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
}
|
||||
else {
|
||||
ibc.imm = instr.imm32;
|
||||
ibc.isrc = &ibc.imm;
|
||||
ibc.memMask = ScratchpadL3Mask;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(IMUL_9C) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
ibc.type = InstructionType::IMUL_9C;
|
||||
ibc.idst = &r[dst];
|
||||
ibc.imm = signExtend2sCompl(instr.imm32);
|
||||
} break;
|
||||
|
||||
CASE_REP(IMUL_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::IMUL_R;
|
||||
ibc.idst = &r[dst];
|
||||
if (src != dst) {
|
||||
ibc.isrc = &r[src];
|
||||
}
|
||||
else {
|
||||
ibc.imm = signExtend2sCompl(instr.imm32);
|
||||
ibc.isrc = &ibc.imm;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(IMUL_M) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::IMUL_M;
|
||||
ibc.idst = &r[dst];
|
||||
if (instr.src != instr.dst) {
|
||||
ibc.isrc = &r[src];
|
||||
ibc.memMask = ((instr.mod % 4) ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
}
|
||||
else {
|
||||
ibc.imm = instr.imm32;
|
||||
ibc.isrc = &ibc.imm;
|
||||
ibc.memMask = ScratchpadL3Mask;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(IMULH_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::IMULH_R;
|
||||
ibc.idst = &r[dst];
|
||||
ibc.isrc = &r[src];
|
||||
} break;
|
||||
|
||||
CASE_REP(IMULH_M) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::IMULH_M;
|
||||
ibc.idst = &r[dst];
|
||||
if (instr.src != instr.dst) {
|
||||
ibc.isrc = &r[src];
|
||||
ibc.memMask = ((instr.mod % 4) ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
}
|
||||
else {
|
||||
ibc.imm = instr.imm32;
|
||||
ibc.isrc = &ibc.imm;
|
||||
ibc.memMask = ScratchpadL3Mask;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(ISMULH_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::ISMULH_R;
|
||||
ibc.idst = &r[dst];
|
||||
ibc.isrc = &r[src];
|
||||
} break;
|
||||
|
||||
CASE_REP(ISMULH_M) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::ISMULH_M;
|
||||
ibc.idst = &r[dst];
|
||||
if (instr.src != instr.dst) {
|
||||
ibc.isrc = &r[src];
|
||||
ibc.memMask = ((instr.mod % 4) ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
}
|
||||
else {
|
||||
ibc.imm = instr.imm32;
|
||||
ibc.isrc = &ibc.imm;
|
||||
ibc.memMask = ScratchpadL3Mask;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(IDIV_C) {
|
||||
uint32_t divisor = instr.imm32;
|
||||
if (divisor != 0) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
ibc.type = InstructionType::IDIV_C;
|
||||
ibc.idst = &r[dst];
|
||||
if (divisor & (divisor - 1)) {
|
||||
magicu_info mi = compute_unsigned_magic_info(divisor, sizeof(uint64_t) * 8);
|
||||
ibc.signedMultiplier = mi.multiplier;
|
||||
ibc.preShift = mi.pre_shift;
|
||||
ibc.postShift = mi.post_shift;
|
||||
ibc.increment = mi.increment;
|
||||
}
|
||||
else {
|
||||
ibc.signedMultiplier = 0;
|
||||
int shift = 0;
|
||||
while (divisor >>= 1)
|
||||
++shift;
|
||||
ibc.shift = shift;
|
||||
}
|
||||
}
|
||||
else {
|
||||
ibc.type = InstructionType::NOP;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(ISDIV_C) {
|
||||
ibc.type = InstructionType::NOP;
|
||||
} break;
|
||||
|
||||
CASE_REP(INEG_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
ibc.type = InstructionType::INEG_R;
|
||||
ibc.idst = &r[dst];
|
||||
} break;
|
||||
|
||||
CASE_REP(IXOR_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::IXOR_R;
|
||||
ibc.idst = &r[dst];
|
||||
if (src != dst) {
|
||||
ibc.isrc = &r[src];
|
||||
}
|
||||
else {
|
||||
ibc.imm = signExtend2sCompl(instr.imm32);
|
||||
ibc.isrc = &ibc.imm;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(IXOR_M) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::IXOR_M;
|
||||
ibc.idst = &r[dst];
|
||||
if (instr.src != instr.dst) {
|
||||
ibc.isrc = &r[src];
|
||||
ibc.memMask = ((instr.mod % 4) ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
}
|
||||
else {
|
||||
ibc.imm = instr.imm32;
|
||||
ibc.isrc = &ibc.imm;
|
||||
ibc.memMask = ScratchpadL3Mask;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(IROR_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::IROR_R;
|
||||
ibc.idst = &r[dst];
|
||||
if (src != dst) {
|
||||
ibc.isrc = &r[src];
|
||||
}
|
||||
else {
|
||||
ibc.imm = instr.imm32;
|
||||
ibc.isrc = &ibc.imm;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(IROL_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::IROL_R;
|
||||
ibc.idst = &r[dst];
|
||||
if (src != dst) {
|
||||
ibc.isrc = &r[src];
|
||||
}
|
||||
else {
|
||||
ibc.imm = instr.imm32;
|
||||
ibc.isrc = &ibc.imm;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(ISWAP_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
if (src != dst) {
|
||||
ibc.idst = &r[dst];
|
||||
ibc.isrc = &r[src];
|
||||
ibc.type = InstructionType::ISWAP_R;
|
||||
}
|
||||
else {
|
||||
ibc.type = InstructionType::NOP;
|
||||
}
|
||||
} break;
|
||||
|
||||
CASE_REP(FSWAP_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
ibc.type = InstructionType::FSWAP_R;
|
||||
ibc.fdst = &f[dst];
|
||||
} break;
|
||||
|
||||
CASE_REP(FADD_R) {
|
||||
auto dst = instr.dst % 4;
|
||||
auto src = instr.src % 4;
|
||||
ibc.type = InstructionType::FADD_R;
|
||||
ibc.fdst = &f[dst];
|
||||
ibc.fsrc = &a[src];
|
||||
} break;
|
||||
|
||||
CASE_REP(FADD_M) {
|
||||
auto dst = instr.dst % 4;
|
||||
auto src = instr.src % 8;
|
||||
ibc.type = InstructionType::FADD_M;
|
||||
ibc.fdst = &f[dst];
|
||||
ibc.isrc = &r[src];
|
||||
ibc.memMask = ((instr.mod % 4) ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
} break;
|
||||
|
||||
CASE_REP(FSUB_R) {
|
||||
auto dst = instr.dst % 4;
|
||||
auto src = instr.src % 4;
|
||||
ibc.type = InstructionType::FSUB_R;
|
||||
ibc.fdst = &f[dst];
|
||||
ibc.fsrc = &a[src];
|
||||
} break;
|
||||
|
||||
CASE_REP(FSUB_M) {
|
||||
auto dst = instr.dst % 4;
|
||||
auto src = instr.src % 8;
|
||||
ibc.type = InstructionType::FSUB_M;
|
||||
ibc.fdst = &f[dst];
|
||||
ibc.isrc = &r[src];
|
||||
ibc.memMask = ((instr.mod % 4) ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
} break;
|
||||
|
||||
CASE_REP(FNEG_R) {
|
||||
auto dst = instr.dst % 4;
|
||||
ibc.fdst = &f[dst];
|
||||
ibc.type = InstructionType::FNEG_R;
|
||||
} break;
|
||||
|
||||
CASE_REP(FMUL_R) {
|
||||
auto dst = instr.dst % 4;
|
||||
auto src = instr.src % 4;
|
||||
ibc.type = InstructionType::FMUL_R;
|
||||
ibc.fdst = &e[dst];
|
||||
ibc.fsrc = &a[src];
|
||||
} break;
|
||||
|
||||
CASE_REP(FMUL_M) {
|
||||
} break;
|
||||
|
||||
CASE_REP(FDIV_R) {
|
||||
} break;
|
||||
|
||||
CASE_REP(FDIV_M) {
|
||||
auto dst = instr.dst % 4;
|
||||
auto src = instr.src % 8;
|
||||
ibc.type = InstructionType::FDIV_M;
|
||||
ibc.fdst = &e[dst];
|
||||
ibc.isrc = &r[src];
|
||||
ibc.memMask = ((instr.mod % 4) ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
} break;
|
||||
|
||||
CASE_REP(FSQRT_R) {
|
||||
auto dst = instr.dst % 4;
|
||||
ibc.type = InstructionType::FSQRT_R;
|
||||
ibc.fdst = &e[dst];
|
||||
} break;
|
||||
|
||||
CASE_REP(COND_R) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::COND_R;
|
||||
ibc.idst = &r[dst];
|
||||
ibc.isrc = &r[src];
|
||||
ibc.condition = (instr.mod >> 2) & 7;
|
||||
ibc.imm = instr.imm32;
|
||||
} break;
|
||||
|
||||
CASE_REP(COND_M) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::COND_M;
|
||||
ibc.idst = &r[dst];
|
||||
ibc.isrc = &r[src];
|
||||
ibc.condition = (instr.mod >> 2) & 7;
|
||||
ibc.imm = instr.imm32;
|
||||
ibc.memMask = ((instr.mod % 4) ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
} break;
|
||||
|
||||
CASE_REP(CFROUND) {
|
||||
auto src = instr.src % 8;
|
||||
ibc.isrc = &r[src];
|
||||
ibc.type = InstructionType::CFROUND;
|
||||
ibc.imm = instr.imm32 & 63;
|
||||
} break;
|
||||
|
||||
CASE_REP(ISTORE) {
|
||||
auto dst = instr.dst % RegistersCount;
|
||||
auto src = instr.src % RegistersCount;
|
||||
ibc.type = InstructionType::ISTORE;
|
||||
ibc.idst = &r[dst];
|
||||
ibc.isrc = &r[src];
|
||||
} break;
|
||||
|
||||
CASE_REP(FSTORE) {
|
||||
} break;
|
||||
|
||||
CASE_REP(NOP) {
|
||||
ibc.type = InstructionType::NOP;
|
||||
} break;
|
||||
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
InstructionHandler InterpretedVirtualMachine::engine[256] = {
|
||||
|
||||
};
|
||||
}
|
||||
Reference in New Issue
Block a user