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https://codeberg.org/wownero/RandomWOW
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Regression tests (#73)
* instruction decode/execute separated into class BytecodeMachine * added randomx-tests project * removed the use of non-portable __COUNTER__ macro * removed the use of unsupported FENV_ACCESS pragma
This commit is contained in:
tevador
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src/bytecode_machine.hpp
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322
src/bytecode_machine.hpp
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/*
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Copyright (c) 2019, tevador <tevador@gmail.com>
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the copyright holder nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#pragma once
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#include "common.hpp"
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#include "intrin_portable.h"
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#include "instruction.hpp"
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#include "program.hpp"
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namespace randomx {
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//register file in machine byte order
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struct NativeRegisterFile {
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int_reg_t r[RegistersCount] = { 0 };
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rx_vec_f128 f[RegisterCountFlt];
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rx_vec_f128 e[RegisterCountFlt];
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rx_vec_f128 a[RegisterCountFlt];
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};
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struct InstructionByteCode {
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union {
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int_reg_t* idst;
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rx_vec_f128* fdst;
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};
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union {
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const int_reg_t* isrc;
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const rx_vec_f128* fsrc;
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};
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union {
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uint64_t imm;
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int64_t simm;
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};
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InstructionType type;
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union {
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int16_t target;
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uint16_t shift;
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};
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uint32_t memMask;
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};
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#define OPCODE_CEIL_DECLARE(curr, prev) constexpr int ceil_ ## curr = ceil_ ## prev + RANDOMX_FREQ_ ## curr;
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constexpr int ceil_NULL = 0;
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OPCODE_CEIL_DECLARE(IADD_RS, NULL);
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OPCODE_CEIL_DECLARE(IADD_M, IADD_RS);
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OPCODE_CEIL_DECLARE(ISUB_R, IADD_M);
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OPCODE_CEIL_DECLARE(ISUB_M, ISUB_R);
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OPCODE_CEIL_DECLARE(IMUL_R, ISUB_M);
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OPCODE_CEIL_DECLARE(IMUL_M, IMUL_R);
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OPCODE_CEIL_DECLARE(IMULH_R, IMUL_M);
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OPCODE_CEIL_DECLARE(IMULH_M, IMULH_R);
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OPCODE_CEIL_DECLARE(ISMULH_R, IMULH_M);
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OPCODE_CEIL_DECLARE(ISMULH_M, ISMULH_R);
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OPCODE_CEIL_DECLARE(IMUL_RCP, ISMULH_M);
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OPCODE_CEIL_DECLARE(INEG_R, IMUL_RCP);
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OPCODE_CEIL_DECLARE(IXOR_R, INEG_R);
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OPCODE_CEIL_DECLARE(IXOR_M, IXOR_R);
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OPCODE_CEIL_DECLARE(IROR_R, IXOR_M);
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OPCODE_CEIL_DECLARE(IROL_R, IROR_R);
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OPCODE_CEIL_DECLARE(ISWAP_R, IROL_R);
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OPCODE_CEIL_DECLARE(FSWAP_R, ISWAP_R);
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OPCODE_CEIL_DECLARE(FADD_R, FSWAP_R);
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OPCODE_CEIL_DECLARE(FADD_M, FADD_R);
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OPCODE_CEIL_DECLARE(FSUB_R, FADD_M);
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OPCODE_CEIL_DECLARE(FSUB_M, FSUB_R);
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OPCODE_CEIL_DECLARE(FSCAL_R, FSUB_M);
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OPCODE_CEIL_DECLARE(FMUL_R, FSCAL_R);
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OPCODE_CEIL_DECLARE(FDIV_M, FMUL_R);
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OPCODE_CEIL_DECLARE(FSQRT_R, FDIV_M);
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OPCODE_CEIL_DECLARE(CBRANCH, FSQRT_R);
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OPCODE_CEIL_DECLARE(CFROUND, CBRANCH);
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OPCODE_CEIL_DECLARE(ISTORE, CFROUND);
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OPCODE_CEIL_DECLARE(NOP, ISTORE);
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#undef OPCODE_CEIL_DECLARE
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#define RANDOMX_EXE_ARGS InstructionByteCode& ibc, int& pc, uint8_t* scratchpad, ProgramConfiguration& config
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#define RANDOMX_GEN_ARGS Instruction& instr, int i, InstructionByteCode& ibc
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class BytecodeMachine;
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typedef void(BytecodeMachine::*InstructionGenBytecode)(RANDOMX_GEN_ARGS);
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class BytecodeMachine {
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public:
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void beginCompilation(NativeRegisterFile& regFile) {
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for (unsigned i = 0; i < RegistersCount; ++i) {
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registerUsage[i] = -1;
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}
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nreg = ®File;
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}
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void compileProgram(Program& program, InstructionByteCode bytecode[RANDOMX_PROGRAM_SIZE], NativeRegisterFile& regFile) {
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beginCompilation(regFile);
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for (unsigned i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) {
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auto& instr = program(i);
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auto& ibc = bytecode[i];
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compileInstruction(instr, i, ibc);
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}
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}
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static void executeBytecode(InstructionByteCode bytecode[RANDOMX_PROGRAM_SIZE], uint8_t* scratchpad, ProgramConfiguration& config) {
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for (int pc = 0; pc < RANDOMX_PROGRAM_SIZE; ++pc) {
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auto& ibc = bytecode[pc];
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executeInstruction(ibc, pc, scratchpad, config);
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}
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}
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void compileInstruction(RANDOMX_GEN_ARGS)
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#ifdef RANDOMX_GEN_TABLE
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{
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auto generator = genTable[instr.opcode];
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(this->*generator)(instr, i, ibc);
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}
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#else
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;
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#endif
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static void executeInstruction(RANDOMX_EXE_ARGS);
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static void exe_IADD_RS(RANDOMX_EXE_ARGS) {
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*ibc.idst += (*ibc.isrc << ibc.shift) + ibc.imm;
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}
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static void exe_IADD_M(RANDOMX_EXE_ARGS) {
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*ibc.idst += load64(getScratchpadAddress(ibc, scratchpad));
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}
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static void exe_ISUB_R(RANDOMX_EXE_ARGS) {
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*ibc.idst -= *ibc.isrc;
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}
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static void exe_ISUB_M(RANDOMX_EXE_ARGS) {
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*ibc.idst -= load64(getScratchpadAddress(ibc, scratchpad));
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}
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static void exe_IMUL_R(RANDOMX_EXE_ARGS) {
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*ibc.idst *= *ibc.isrc;
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}
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static void exe_IMUL_M(RANDOMX_EXE_ARGS) {
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*ibc.idst *= load64(getScratchpadAddress(ibc, scratchpad));
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}
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static void exe_IMULH_R(RANDOMX_EXE_ARGS) {
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*ibc.idst = mulh(*ibc.idst, *ibc.isrc);
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}
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static void exe_IMULH_M(RANDOMX_EXE_ARGS) {
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*ibc.idst = mulh(*ibc.idst, load64(getScratchpadAddress(ibc, scratchpad)));
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}
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static void exe_ISMULH_R(RANDOMX_EXE_ARGS) {
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*ibc.idst = smulh(unsigned64ToSigned2sCompl(*ibc.idst), unsigned64ToSigned2sCompl(*ibc.isrc));
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}
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static void exe_ISMULH_M(RANDOMX_EXE_ARGS) {
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*ibc.idst = smulh(unsigned64ToSigned2sCompl(*ibc.idst), unsigned64ToSigned2sCompl(load64(getScratchpadAddress(ibc, scratchpad))));
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}
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static void exe_INEG_R(RANDOMX_EXE_ARGS) {
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*ibc.idst = ~(*ibc.idst) + 1; //two's complement negative
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}
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static void exe_IXOR_R(RANDOMX_EXE_ARGS) {
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*ibc.idst ^= *ibc.isrc;
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}
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static void exe_IXOR_M(RANDOMX_EXE_ARGS) {
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*ibc.idst ^= load64(getScratchpadAddress(ibc, scratchpad));
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}
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static void exe_IROR_R(RANDOMX_EXE_ARGS) {
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*ibc.idst = rotr(*ibc.idst, *ibc.isrc & 63);
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}
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static void exe_IROL_R(RANDOMX_EXE_ARGS) {
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*ibc.idst = rotl(*ibc.idst, *ibc.isrc & 63);
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}
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static void exe_ISWAP_R(RANDOMX_EXE_ARGS) {
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int_reg_t temp = *ibc.isrc;
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*(int_reg_t*)ibc.isrc = *ibc.idst;
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*ibc.idst = temp;
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}
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static void exe_FSWAP_R(RANDOMX_EXE_ARGS) {
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*ibc.fdst = rx_swap_vec_f128(*ibc.fdst);
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}
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static void exe_FADD_R(RANDOMX_EXE_ARGS) {
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*ibc.fdst = rx_add_vec_f128(*ibc.fdst, *ibc.fsrc);
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}
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static void exe_FADD_M(RANDOMX_EXE_ARGS) {
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rx_vec_f128 fsrc = rx_cvt_packed_int_vec_f128(getScratchpadAddress(ibc, scratchpad));
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*ibc.fdst = rx_add_vec_f128(*ibc.fdst, fsrc);
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}
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static void exe_FSUB_R(RANDOMX_EXE_ARGS) {
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*ibc.fdst = rx_sub_vec_f128(*ibc.fdst, *ibc.fsrc);
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}
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static void exe_FSUB_M(RANDOMX_EXE_ARGS) {
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rx_vec_f128 fsrc = rx_cvt_packed_int_vec_f128(getScratchpadAddress(ibc, scratchpad));
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*ibc.fdst = rx_sub_vec_f128(*ibc.fdst, fsrc);
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}
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static void exe_FSCAL_R(RANDOMX_EXE_ARGS) {
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const rx_vec_f128 mask = rx_set1_vec_f128(0x80F0000000000000);
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*ibc.fdst = rx_xor_vec_f128(*ibc.fdst, mask);
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}
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static void exe_FMUL_R(RANDOMX_EXE_ARGS) {
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*ibc.fdst = rx_mul_vec_f128(*ibc.fdst, *ibc.fsrc);
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}
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static void exe_FDIV_M(RANDOMX_EXE_ARGS) {
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rx_vec_f128 fsrc = maskRegisterExponentMantissa(
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config,
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rx_cvt_packed_int_vec_f128(getScratchpadAddress(ibc, scratchpad))
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);
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*ibc.fdst = rx_div_vec_f128(*ibc.fdst, fsrc);
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}
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static void exe_FSQRT_R(RANDOMX_EXE_ARGS) {
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*ibc.fdst = rx_sqrt_vec_f128(*ibc.fdst);
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}
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static void exe_CBRANCH(RANDOMX_EXE_ARGS) {
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*ibc.idst += ibc.imm;
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if ((*ibc.idst & ibc.memMask) == 0) {
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pc = ibc.target;
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}
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}
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static void exe_CFROUND(RANDOMX_EXE_ARGS) {
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rx_set_rounding_mode(rotr(*ibc.isrc, ibc.imm) % 4);
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}
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static void exe_ISTORE(RANDOMX_EXE_ARGS) {
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store64(scratchpad + ((*ibc.idst + ibc.imm) & ibc.memMask), *ibc.isrc);
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}
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protected:
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static rx_vec_f128 maskRegisterExponentMantissa(ProgramConfiguration& config, rx_vec_f128 x) {
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const rx_vec_f128 xmantissaMask = rx_set_vec_f128(dynamicMantissaMask, dynamicMantissaMask);
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const rx_vec_f128 xexponentMask = rx_load_vec_f128((const double*)&config.eMask);
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x = rx_and_vec_f128(x, xmantissaMask);
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x = rx_or_vec_f128(x, xexponentMask);
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return x;
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}
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private:
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static const int_reg_t zero;
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int registerUsage[RegistersCount];
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NativeRegisterFile* nreg;
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static void* getScratchpadAddress(InstructionByteCode& ibc, uint8_t* scratchpad) {
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uint32_t addr = (*ibc.isrc + ibc.imm) & ibc.memMask;
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return scratchpad + addr;
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}
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#ifdef RANDOMX_GEN_TABLE
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static InstructionGenBytecode genTable[256];
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void gen_IADD_RS(RANDOMX_GEN_ARGS);
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void gen_IADD_M(RANDOMX_GEN_ARGS);
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void gen_ISUB_R(RANDOMX_GEN_ARGS);
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void gen_ISUB_M(RANDOMX_GEN_ARGS);
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void gen_IMUL_R(RANDOMX_GEN_ARGS);
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void gen_IMUL_M(RANDOMX_GEN_ARGS);
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void gen_IMULH_R(RANDOMX_GEN_ARGS);
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void gen_IMULH_M(RANDOMX_GEN_ARGS);
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void gen_ISMULH_R(RANDOMX_GEN_ARGS);
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void gen_ISMULH_M(RANDOMX_GEN_ARGS);
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void gen_IMUL_RCP(RANDOMX_GEN_ARGS);
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void gen_INEG_R(RANDOMX_GEN_ARGS);
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void gen_IXOR_R(RANDOMX_GEN_ARGS);
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void gen_IXOR_M(RANDOMX_GEN_ARGS);
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void gen_IROR_R(RANDOMX_GEN_ARGS);
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void gen_IROL_R(RANDOMX_GEN_ARGS);
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void gen_ISWAP_R(RANDOMX_GEN_ARGS);
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void gen_FSWAP_R(RANDOMX_GEN_ARGS);
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void gen_FADD_R(RANDOMX_GEN_ARGS);
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void gen_FADD_M(RANDOMX_GEN_ARGS);
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void gen_FSUB_R(RANDOMX_GEN_ARGS);
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void gen_FSUB_M(RANDOMX_GEN_ARGS);
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void gen_FSCAL_R(RANDOMX_GEN_ARGS);
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void gen_FMUL_R(RANDOMX_GEN_ARGS);
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void gen_FDIV_M(RANDOMX_GEN_ARGS);
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void gen_FSQRT_R(RANDOMX_GEN_ARGS);
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void gen_CBRANCH(RANDOMX_GEN_ARGS);
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void gen_CFROUND(RANDOMX_GEN_ARGS);
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void gen_ISTORE(RANDOMX_GEN_ARGS);
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void gen_NOP(RANDOMX_GEN_ARGS);
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#endif
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};
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}
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