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https://codeberg.org/wownero/RandomWOW
synced 2026-03-06 06:37:33 -05:00
Added explicit STORE instructions
JIT compiler
This commit is contained in:
tevador
@@ -30,16 +30,10 @@ namespace RandomX {
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class JitCompilerX86;
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typedef void(JitCompilerX86::*InstructionGeneratorX86)(Instruction&, int);
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typedef void(JitCompilerX86::*InstructionGeneratorX86)(Instruction&);
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constexpr uint32_t CodeSize = 64 * 1024;
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struct CallOffset {
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CallOffset(int32_t p, int32_t i) : pos(p), index(i) {}
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int32_t pos;
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int32_t index;
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};
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class JitCompilerX86 {
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public:
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JitCompilerX86();
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@@ -55,66 +49,82 @@ namespace RandomX {
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static InstructionGeneratorX86 engine[256];
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uint8_t* code;
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int32_t codePos;
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std::vector<int32_t> instructionOffsets;
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std::vector<CallOffset> callOffsets;
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void gena(Instruction&);
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void genar(Instruction&);
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void genaf(Instruction&);
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void genbiashift(Instruction&, uint16_t, uint16_t);
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void genbia(Instruction&, uint16_t, uint16_t);
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void genbia32(Instruction&, uint16_t, uint8_t);
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void genbf(Instruction&, uint8_t);
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void scratchpadStoreR(Instruction&, uint32_t, bool);
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void scratchpadStoreF(Instruction&, int, uint32_t, bool);
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void gencr(Instruction&, bool);
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void gencf(Instruction&);
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void generateCode(Instruction&, int);
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void fixCallOffsets();
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void genAddressReg(Instruction&, bool);
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void genAddressRegDst(Instruction&, bool);
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void genAddressImm(Instruction&);
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void genSIB(int scale, int index, int base);
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void generateCode(Instruction&);
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void emitByte(uint8_t val) {
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code[codePos] = val;
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codePos++;
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}
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template<typename T>
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void emit(T val) {
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*reinterpret_cast<T*>(code + codePos) = val;
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codePos += sizeof(T);
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void emit32(uint32_t val) {
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code[codePos + 0] = val;
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code[codePos + 1] = val >> 8;
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code[codePos + 2] = val >> 16;
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code[codePos + 3] = val >> 24;
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codePos += 4;
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}
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void h_ADD_64(Instruction&, int);
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void h_ADD_32(Instruction&, int);
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void h_SUB_64(Instruction&, int);
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void h_SUB_32(Instruction&, int);
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void h_MUL_64(Instruction&, int);
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void h_MULH_64(Instruction&, int);
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void h_MUL_32(Instruction&, int);
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void h_IMUL_32(Instruction&, int);
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void h_IMULH_64(Instruction&, int);
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void h_DIV_64(Instruction&, int);
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void h_IDIV_64(Instruction&, int);
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void h_AND_64(Instruction&, int);
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void h_AND_32(Instruction&, int);
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void h_OR_64(Instruction&, int);
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void h_OR_32(Instruction&, int);
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void h_XOR_64(Instruction&, int);
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void h_XOR_32(Instruction&, int);
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void h_SHL_64(Instruction&, int);
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void h_SHR_64(Instruction&, int);
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void h_SAR_64(Instruction&, int);
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void h_ROL_64(Instruction&, int);
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void h_ROR_64(Instruction&, int);
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void h_FPADD(Instruction&, int);
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void h_FPSUB(Instruction&, int);
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void h_FPMUL(Instruction&, int);
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void h_FPDIV(Instruction&, int);
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void h_FPSQRT(Instruction&, int);
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void h_FPROUND(Instruction&, int);
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void h_JUMP(Instruction&, int);
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void h_CALL(Instruction&, int);
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void h_RET(Instruction&, int);
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void h_NOP(Instruction&, int);
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void emit64(uint64_t val) {
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code[codePos + 0] = val;
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code[codePos + 1] = val >> 8;
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code[codePos + 2] = val >> 16;
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code[codePos + 3] = val >> 24;
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code[codePos + 4] = val >> 32;
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code[codePos + 5] = val >> 40;
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code[codePos + 6] = val >> 48;
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code[codePos + 7] = val >> 56;
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codePos += 8;
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}
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template<size_t N>
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void emit(const uint8_t (&src)[N]) {
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for (int i = 0; i < N; ++i) {
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code[codePos + i] = src[i];
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}
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codePos += N;
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}
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void h_IADD_R(Instruction&);
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void h_IADD_M(Instruction&);
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void h_IADD_RC(Instruction&);
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void h_ISUB_R(Instruction&);
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void h_ISUB_M(Instruction&);
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void h_IMUL_9C(Instruction&);
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void h_IMUL_R(Instruction&);
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void h_IMUL_M(Instruction&);
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void h_IMULH_R(Instruction&);
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void h_IMULH_M(Instruction&);
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void h_ISMULH_R(Instruction&);
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void h_ISMULH_M(Instruction&);
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void h_IDIV_C(Instruction&);
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void h_ISDIV_C(Instruction&);
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void h_INEG_R(Instruction&);
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void h_IXOR_R(Instruction&);
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void h_IXOR_M(Instruction&);
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void h_IROR_R(Instruction&);
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void h_IROL_R(Instruction&);
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void h_FPSWAP_R(Instruction&);
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void h_FPADD_R(Instruction&);
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void h_FPADD_M(Instruction&);
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void h_FPSUB_R(Instruction&);
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void h_FPSUB_M(Instruction&);
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void h_FPNEG_R(Instruction&);
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void h_FPMUL_R(Instruction&);
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void h_FPMUL_M(Instruction&);
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void h_FPDIV_R(Instruction&);
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void h_FPDIV_M(Instruction&);
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void h_FPSQRT_R(Instruction&);
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void h_COND_R(Instruction&);
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void h_COND_M(Instruction&);
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void h_CFROUND(Instruction&);
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void h_ISTORE(Instruction&);
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void h_FSTORE(Instruction&);
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};
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}
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